公开(公告)号：US10734049B2

公开(公告)日：2020-08-04

申请号：US16237346

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/00 ,  G11C8/10 ,  G11C7/02 ,  G11C8/12 ,  G11C8/16 ,  G11C8/18 ,  G11C5/02 ,  G11C5/06 ,  G11C11/408 ,  G11C7/00 ,  G11C13/00

Abstract: Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in a memory array are enabled to be accessed at the same time. Additional embodiments are described.

公开(公告)号：US10692870B2

公开(公告)日：2020-06-23

申请号：US15670864

申请日：2017-08-07

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L27/108 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11578 ,  H01L21/74 ,  H01L27/02 ,  H01L27/11

Abstract: Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed substantially within a cavity of a substrate. Peripheral circuitry can be formed adjacent to a surface of the substrate and adjacent to the memory array. Additional apparatuses and methods are described.

公开(公告)号：US10510420B2

公开(公告)日：2019-12-17

申请号：US16141717

申请日：2018-09-25

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/26 ,  G11C16/12 ,  G11C16/10 ,  G11C7/00 ,  G11C16/04 ,  G11C16/34

Abstract: Embodiments are provided that include a memory device having a memory array including a plurality of access lines and data lines. The memory device further includes a circuit coupled to the plurality of access lines and configured to provide consecutive pulses to a selected one of the plurality of access lines. Each pulse of the consecutive pulses includes a first voltage and a second voltage. The first voltage is greater in magnitude than the second voltage, and the first voltage is applied for a shorter duration than the second voltage.

公开(公告)号：US10453538B2

公开(公告)日：2019-10-22

申请号：US16035933

申请日：2018-07-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Koji Sakui ,  Mark Hawes ,  Toru Tanzawa ,  Jeremy Binfet

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/14 ,  G11C16/32 ,  G11C7/04 ,  G11C16/30 ,  G11C16/34 ,  G11C16/20 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/115

Abstract: Apparatus and methods of operating such apparatus include establishing a negative potential in a body of a memory cell in response to a timer, or during an access operation of another memory cell.

公开(公告)号：US20190286777A1

公开(公告)日：2019-09-19

申请号：US16432632

申请日：2019-06-05

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G06F17/50 ,  G11C7/10 ,  G11C29/02 ,  G11C7/22 ,  G11C13/00

Abstract: Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information based at least in part on the measurement of the electrical characteristic. An example apparatus includes a signal line model including a model signal line configured to model electrical characteristics of a signal line. The apparatus further includes a measurement circuit coupled to the signal line model and configured to measure the electrical characteristic of the model signal line responsive to an input signal provided to the model signal line. The measurement circuit is further configured to provide measurement information based at least in part on the measurement to set a signal applied to the signal line.

公开(公告)号：US10366759B2

公开(公告)日：2019-07-30

申请号：US16149261

申请日：2018-10-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: G11C16/04 ,  G11C11/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C16/08 ,  G11C16/32

Abstract: Memory devices include a first string of memory cells selectively connected to a first data line, a second string of memory cells selectively connected to a second data line, and a transistor that selectively connects the first data line to the second data line, thereby permitting connecting the first and second data lines in series before programming or sensing memory cells of the first and second strings of memory cells.

公开(公告)号：US10340015B2

公开(公告)日：2019-07-02

申请号：US16046527

申请日：2018-07-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: G11C7/00 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04 ,  G11C16/30 ,  G11C16/32

Abstract: Apparatuses and methods for charging a global access line prior to accessing memory are described. An example apparatus may include a memory array of a memory. A plurality of global access lines may be associated with the memory array. The global access line may be charged to a ready-access voltage before any access command has been received by the memory. The global access line may be maintained at the ready-access voltage during memory access operations until the receipt of a post-access command. The post-access command may reset the global access line to an inactive voltage.

公开(公告)号：US10262745B2

公开(公告)日：2019-04-16

申请号：US16130324

申请日：2018-09-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa ,  Aaron Yip

IPC: G11C16/28 ,  G11C16/24 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34 ,  G11C7/02 ,  G11C16/04

Abstract: Apparatuses and methods for reducing capacitive loading are described. One apparatus includes a first memory string including first and second dummy memory cells, a second memory string including third and fourth dummy memory cells, and a control unit configured to provide first and second control signals to activate the first and second dummy memory cells of the first memory string and to further deactivate at least one of the third and fourth dummy memory cell of the second memory string.

公开(公告)号：US10262739B2

公开(公告)日：2019-04-16

申请号：US15995626

申请日：2018-06-01

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/08 ,  G11C16/04 ,  G11C8/10 ,  G11C5/02

Abstract: Some embodiments include a device having an array of memory cells, a memory control unit at least partially under the array, row decoder circuitry in data communication with the memory control unit, and column decoder circuitry in data communication with the memory control unit. Some embodiments include a device having an array of memory cells, row decoder circuitry and column decoder circuitry. One of the row and column decoder circuitries is within a unit that extends at least partially under the array of memory cells and the other within a unit that is laterally outward of the array of memory cells.

公开(公告)号：US20190089990A1

公开(公告)日：2019-03-21

申请号：US16197174

申请日：2018-11-20

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H04N19/86 ,  H04N19/80 ,  H04N19/176 ,  H04N19/61 ,  H04N19/182 ,  H04N19/14 ,  H04N19/82 ,  H04N19/117

CPC classification number: H04N19/865 ,  G11C5/063 ,  G11C16/08 ,  G11C16/10 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L2924/0002 ,  H04N19/117 ,  H04N19/14 ,  H04N19/176 ,  H04N19/182 ,  H04N19/61 ,  H04N19/80 ,  H04N19/82 ,  H04N19/86 ,  H01L2924/00

Abstract: Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the apparatus, and a select circuit including a select transistor and a coupling component coupled between the conductive line and the memory cell string. Other embodiments including additional apparatuses and methods are described.