公开(公告)号：US20240096805A1

公开(公告)日：2024-03-21

申请号：US18526445

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Wen Chang ,  Yi-Hsun Chiu ,  Cheng-Chi Chuang ,  Ching-Wei Tsai ,  Wei-Cheng Lin ,  Shih-Wei Peng ,  Jiann-Tyng Tzeng

IPC: H01L23/528 ,  H01L21/02 ,  H01L21/8238 ,  H01L23/00 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L23/5286 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823871 ,  H01L24/05 ,  H01L24/13 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/13026

Abstract: In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.

公开(公告)号：US11916133B2

公开(公告)日：2024-02-27

申请号：US17676699

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Lin-Yu Huang ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/768

CPC classification number: H01L29/6656 ,  H01L21/76832 ,  H01L21/76834 ,  H01L29/66545

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.

公开(公告)号：US20240021707A1

公开(公告)日：2024-01-18

申请号：US18364574

申请日：2023-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Lin-Yu Huang ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/768

CPC classification number: H01L29/6656 ,  H01L21/76832 ,  H01L21/76834 ,  H01L29/66545

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.

公开(公告)号：US11862561B2

公开(公告)日：2024-01-02

申请号：US17126509

申请日：2020-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Wen Chang ,  Yi-Hsun Chiu ,  Cheng-Chi Chuang ,  Ching-Wei Tsai ,  Wei-Cheng Lin ,  Shih-Wei Peng ,  Jiann-Tyng Tzeng

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L23/00

CPC classification number: H01L23/5286 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823871 ,  H01L24/05 ,  H01L24/13 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/13026

Abstract: In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.

公开(公告)号：US20230386905A1

公开(公告)日：2023-11-30

申请号：US18446183

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Chang ,  Lin-Yu Huang ,  Li-Zhen Yu ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L21/76 ,  H01L23/528 ,  H01L23/532 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L21/7682 ,  H01L21/76 ,  H01L21/76834 ,  H01L23/5286 ,  H01L23/53295 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/02172

Abstract: A semiconductor structure includes first and second epitaxial features, at least one semiconductor channel layer connecting the first and second epitaxial features, and a gate structure engaging the semiconductor channel layer. The first and second epitaxial features, the semiconductor channel layer, and the gate structure are at a frontside of the semiconductor structure. The semiconductor structure also includes a backside metal wiring layer at a backside of the semiconductor structure, and a backside conductive contact electrically connecting the first epitaxial feature to the backside metal wiring layer. The backside metal wiring layer is spaced away from the gate structure with an air gap therebetween.

公开(公告)号：US11804486B2

公开(公告)日：2023-10-31

申请号：US17572212

申请日：2022-01-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Huan-Chieh Su ,  Li-Zhen Yu ,  Chun-Yuan Chen ,  Shih-Chuan Chiu ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L21/027 ,  H01L21/308 ,  H01L21/306

CPC classification number: H01L27/0886 ,  H01L21/0274 ,  H01L21/3086 ,  H01L21/30604

Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.

公开(公告)号：US11798884B2

公开(公告)日：2023-10-24

申请号：US17682884

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L21/3213

CPC classification number: H01L23/5283 ,  H01L21/32139 ,  H01L21/76885 ,  H01L23/5226

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes an active region including a channel region and a source/drain region and extending along a first direction, and a source/drain contact structure over the source/drain region. The source/drain contact structure includes a base portion extending lengthwise along a second direction perpendicular to the first direction, and a via portion over the base portion. The via portion tapers away from the base portion.

公开(公告)号：US20230326983A1

公开(公告)日：2023-10-12

申请号：US18329126

申请日：2023-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/28 ,  H01L21/8234 ,  H01L29/417

CPC classification number: H01L29/41725 ,  H01L21/28097 ,  H01L21/28158 ,  H01L21/823475

Abstract: A device includes a substrate, an isolation structure over the substrate, a gate structure over the isolation structure, a gate spacer on a sidewall of the gate structure, a source/drain (S/D) region adjacent to the gate spacer, a silicide on the S/D region, a dielectric liner over a sidewall of the gate spacer and on a top surface of the isolation structure, wherein a bottom surface of the dielectric liner is above a top surface of the silicide layer and spaced away from the top surface of the silicide layer in a cross-sectional plane perpendicular to a lengthwise direction of the gate structure.

公开(公告)号：US11749728B2

公开(公告)日：2023-09-05

申请号：US17401970

申请日：2021-08-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/40 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L21/285 ,  H01L27/088 ,  H01L27/092 ,  H01L21/3213 ,  H01L21/8234

CPC classification number: H01L29/41725 ,  H01L21/0228 ,  H01L21/28556 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/66545 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468

Abstract: A method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening.

公开(公告)号：US11742385B2

公开(公告)日：2023-08-29

申请号：US17750600

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/78 ,  H01L23/528

CPC classification number: H01L29/0843 ,  H01L29/0649 ,  H01L29/785 ,  H01L23/528

Abstract: A semiconductor structure includes a source/drain (S/D) feature; one or more channel semiconductor layers connected to the S/D feature; a gate structure engaging the one or more channel semiconductor layers; a first silicide feature at a frontside of the S/D feature; a second silicide feature at a backside of the S/D feature; and a dielectric liner layer at the backside of the S/D feature, below the second silicide feature, and spaced away from the second silicide feature by a first gap.