公开(公告)号：US09929146B2

公开(公告)日：2018-03-27

申请号：US15454788

申请日：2017-03-09

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Olivier Weber ,  Emmanuel Richard ,  Philippe Boivin

IPC: H01L27/06 ,  H01L29/732 ,  H01L21/84 ,  H01L21/8249 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L21/84 ,  H01L27/1207 ,  H01L27/2445 ,  H01L29/0813 ,  H01L29/41708 ,  H01L29/66303 ,  H01L29/732 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/16

Abstract: Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar transistors: an insulating region including the insulating layer is formed; openings are etched through the insulating region to delimit insulating walls; the openings are filled with first epitaxial portions; and the first epitaxial portions and a first region extending under the first epitaxial portions and under the insulating walls are doped. On the side of the bipolar transistors and on a side of the MOS transistors: gate structures are formed; second epitaxial portions are made; and the second epitaxial portions covering the first epitaxial portions are doped.

公开(公告)号：US20180063638A1

公开(公告)日：2018-03-01

申请号：US15473812

申请日：2017-03-30

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics Design and Application S.R.O. ,  STMicroelectronics (Alps) SAS

Inventor： Jean Claude Bini ,  Dragos Davidescu ,  Igor Cesko ,  Jonathan Cottinet

IPC: H04R3/00 ,  H04R3/04

CPC classification number: H04R3/005 ,  G10K11/346 ,  H04R1/406 ,  H04R3/04 ,  H04R19/005 ,  H04R2201/003 ,  H04R2430/23

Abstract: Several first digital streams of first digital samples at a first sampling frequency are processed to issue corresponding stream that are converted into second digital streams sampled at a second sampling frequency lower than said first sampling frequency. At least one delay to be applied to at least one first digital stream to satisfy a condition on the second digital streams is determined and applied to at least one first digital stream before converting. The converting operation performed is decimation filtering of the first digital streams. The application of the at least one delay to at least one first steam involves skipping a number of first digital samples in the at least one first digital stream. The number skipped depends on the value of the at least one delay. Samples that are skipped are not delivered for decimation filtering.

公开(公告)号：US20180060566A1

公开(公告)日：2018-03-01

申请号：US15442303

申请日：2017-02-24

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Ibrahima Diop ,  Pierre-Yvan Liardet ,  Yanis Linge

IPC: G06F21/52 ,  G06F7/72 ,  G06F7/523

CPC classification number: G06F21/52 ,  G06F7/523 ,  G06F7/72 ,  G06F7/723 ,  G06F2207/7242 ,  G06F2221/032

Abstract: A method of protecting a modular calculation on a first number and a second number, executed by an electronic circuit, including the steps of: combining the second number with a third number to obtain a fourth number; executing the modular calculation on the first and fourth numbers, the result being contained in a first register or memory location; initializing a second register or memory location to the value of the first register or to one; and successively, for each bit at state 1 of the third number: if the corresponding bit of the fourth number is at state 1, multiplying the content of the second register or memory location by the inverse of the first number and placing the result in the first register or memory location, if the corresponding bit of the fourth number is at state 0, multiplying the content of the second register or memory location by the first number and placing the result in the first register or memory location.

公开(公告)号：US09900151B2

公开(公告)日：2018-02-20

申请号：US15056844

申请日：2016-02-29

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Fabrice Marinet ,  Mathieu Lisart

IPC: G06F11/30 ,  G06F12/14 ,  H04L9/08 ,  G06F21/78 ,  G06F11/14 ,  G06F21/62 ,  G06F21/77 ,  G06F3/06

CPC classification number: H04L9/088 ,  G06F3/0623 ,  G06F3/0644 ,  G06F3/0688 ,  G06F11/1458 ,  G06F12/1408 ,  G06F21/62 ,  G06F21/77 ,  G06F21/78 ,  G06F2212/402

Abstract: A method for processing content stored on a component is disclosed. A first partition of a first memory is encrypted with a first encryption key and a second partition of the first memory is encrypted with a second encryption key. The second encryption key is different from the first encryption key. The first encryption key is stored in a storage register of the component and the second encryption key is stored in a first location of a non-volatile memory. A memory address of the first location is stored in the first partition of the first memory.

公开(公告)号：US20180041024A1

公开(公告)日：2018-02-08

申请号：US15436186

申请日：2017-02-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Nicolas Demange

IPC: H02H7/125 ,  H01L27/02 ,  H02H7/20

CPC classification number: H02H7/1252 ,  G06K19/0701 ,  G06K19/07735 ,  H01L27/0255 ,  H02H7/20 ,  H02H9/041 ,  H02H9/046

Abstract: An integrated circuit includes a voltage regulating circuit in the form of only one transistor, or a group of several transistors in parallel, that are connected between first and second terminals configured to be coupled to an antenna. A control circuit operates to make the voltage regulating circuit inactive when a pulse generated by an electrostatic discharge event appears at one of the first and second terminals, regardless of the direction of flow of the pulse between the first and second terminals. An electrostatic discharge circuit is further provided to address the electrostatic discharge event.

公开(公告)号：US09886380B2

公开(公告)日：2018-02-06

申请号：US15141048

申请日：2016-04-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christophe Arnal ,  Roland Van Der Tuijn

IPC: G06F12/00 ,  G06F12/06 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/02 ,  G06F12/1009

CPC classification number: G06F12/0646 ,  G06F3/0644 ,  G06F9/5077 ,  G06F12/023 ,  G06F12/0284 ,  G06F12/0802 ,  G06F12/1009 ,  G06F2212/1041 ,  G06F2212/151 ,  G06F2212/657

Abstract: A virtual memory is partitioned into virtual partitions, each partition being subdivided into virtual sub-partitions and each sub-partition corresponding to a combination of multiple sectors of identical or different sizes of a physical memory. When an allocation request is made for a virtual memory space having a given memory size, a free partition is selected, a virtual sub-partition is selected corresponding to a combination of sectors having a minimum total size covering the given memory size of the virtual memory to be allocated, and free sectors of the physical memory are selected corresponding to the selected combination. A determination is made of a correspondence table between the selected virtual partition and the initial physical addresses of the selected free sectors, and a virtual address is generated.

公开(公告)号：US20180034497A1

公开(公告)日：2018-02-01

申请号：US15728150

申请日：2017-10-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Tramoni

IPC: H04B1/40 ,  H04B5/00 ,  H04B1/18

CPC classification number: H04B1/40 ,  H04B1/0458 ,  H04B1/18 ,  H04B5/0025

Abstract: A contactless component, connected to an antenna, includes a plurality of terminals and a first, second, third, and fourth plurality of switchable auxiliary capacitors. The plurality of terminals include a first output terminal, a second output terminal, a first auxiliary terminal, and a second auxiliary terminal. Each of the first plurality of switchable auxiliary capacitors is connected between the first auxiliary terminal and the first output terminal. Each of the second plurality of switchable auxiliary capacitors is coupled between the first auxiliary terminal and a neutral point. Each of the third plurality of switchable auxiliary capacitors is coupled between the second auxiliary terminal and the second output terminal of the contactless component. Each of the fourth plurality of switchable auxiliary capacitors is coupled between the second auxiliary terminal and the neutral point.

公开(公告)号：US20180033878A1

公开(公告)日：2018-02-01

申请号：US15436819

申请日：2017-02-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: H01L29/74 ,  H01L29/866 ,  H01L27/02

CPC classification number: H01L29/7412 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0262 ,  H01L29/7408 ,  H01L29/866 ,  H02H9/046

Abstract: An integrated circuit includes at least one input-output pad and a terminal intended to be connected to a source of a reference potential and further including a protection structure including a thyristor forward-connected between the pad and the terminal. The thyristor includes a first resistor between its cathode gate and the terminal. At least one Zener diode is disposed between the thyristor and the pad. The anode of the Zener diode is connected to the cathode gate of the thyristor and the cathode of the Zener diode is connected to the pad via at least one second resistor. The junction of the Zener diode is different from the junctions of the PNPN structure of the thyristor.

公开(公告)号：US09838077B2

公开(公告)日：2017-12-05

申请号：US15042509

申请日：2016-02-12

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Pierre Demaj ,  Yoann Bouvet

IPC: H04B3/54 ,  H04L5/00 ,  H04L27/26

CPC classification number: H04B3/54 ,  H04L5/0007 ,  H04L5/0044 ,  H04L27/2601 ,  H04L27/2647

Abstract: A method is for processing an analog channel signal from a transmission channel. The analog channel signal conveys frames, the transmission channel being linear and cyclostationary for a duration of a frame. The method may include converting of the analog channel signal into a digital channel signal, and performing channel estimations for the frame based upon the digital channel signal to generate a sequence of N transfer functions of the transmission channel. Each of the sequence of N transfer functions may be respectively associated with N successive time slices. The method may include decoding at least some symbols of the frame using, for each of the symbols, a transfer function associated with a successive time slice including a respective symbol.

公开(公告)号：US09836070B2

公开(公告)日：2017-12-05

申请号：US14937671

申请日：2015-11-10

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Jimmy Fort ,  Thierry Soude

IPC: G05F1/575 ,  H03F3/45

CPC classification number: G05F1/575 ,  H03F3/45179

Abstract: The regulator with a low dropout voltage comprises an error amplifier comprising a differential pair of input transistors and a circuit with folded cascode structure connected to the output of the said differential pair, an output stage connected to the output node of the error amplifier, and a Miller compensation capacitor connected between the output stage and the cascode node on the output side (XP) of the cascode circuit; the error amplifier furthermore comprises at least one inverting amplifier module in a feedback loop between the said cascode node and the gate of the cascode transistor of the cascode circuit connected between the said cascode node and the said output node.