公开(公告)号：US20180102395A1

公开(公告)日：2018-04-12

申请号：US15829397

申请日：2017-12-01

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528

CPC classification number: H01L27/2436 ,  H01L23/528 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1633 ,  H01L45/1691

Abstract: A memory cell includes a substrate layer, with a plurality of silicided semiconductor fins stacked on the substrate layer and spaced apart from one another. A first metal liner layer is stacked on the plurality of silicided semiconductor fins and on the substrate layer. A plurality of first contact pillars are stacked on the first metal liner layer adjacent a different respective one of the plurality of silicided semiconductor fins. A configurable resistance structure covers portions of the first metal liner layer that are stacked on the substrate layer and portions of the first metal liner layer that are stacked on each of the plurality of silicided semiconductor fins. A metal fill layer is stacked on the configurable resistance structure. A plurality of second contact pillars is stacked on the metal fill layer adjacent a space between a different pair of adjacent silicided semiconductor fins of the plurality thereof.

公开(公告)号：US09917020B2

公开(公告)日：2018-03-13

申请号：US15238559

申请日：2016-08-16

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L27/12 ,  H01L27/02 ,  H01L21/84 ,  H01L21/266 ,  H01L21/265 ,  H01L21/308 ,  H01L29/06 ,  H01L29/10 ,  H01L29/161 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/845 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/3081 ,  H01L27/0207 ,  H01L27/1211 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/4236 ,  H01L29/66795

Abstract: An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.

公开(公告)号：US09748369B2

公开(公告)日：2017-08-29

申请号：US15258412

申请日：2016-09-07

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu

IPC: H01L29/735 ,  H01L29/66 ,  H01L21/285 ,  H01L29/08 ,  H01L29/45 ,  H01L29/423 ,  H01L29/73 ,  H01L29/10

CPC classification number: H01L29/735 ,  H01L21/28506 ,  H01L21/28518 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/42304 ,  H01L29/456 ,  H01L29/6625 ,  H01L29/66257 ,  H01L29/7317

Abstract: A bipolar transistor is supported by a substrate including a semiconductor layer overlying an insulating layer. A transistor base is formed by a base region in the semiconductor layer that is doped with a first conductivity type dopant at a first dopant concentration. The transistor emitter and collector are formed by regions doped with a second conductivity type dopant and located adjacent opposite sides of the base region. An extrinsic base includes an epitaxial semiconductor layer in contact with a top surface of the base region. The epitaxial semiconductor layer is doped with the first conductivity type dopant at a second dopant concentration greater than the first dopant concentration. Sidewall spacers on each side of the extrinsic base include an oxide liner on a side of the epitaxial semiconductor layer and the top surface of the base region.

公开(公告)号：US09543436B2

公开(公告)日：2017-01-10

申请号：US14942566

申请日：2015-11-16

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Qing Liu ,  Thomas Skotnicki

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L27/12 ,  H01L29/423

CPC classification number: H01L29/7838 ,  H01L21/28114 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834

Abstract: An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material.

Abstract translation: 集成电路管芯包括具有第一半导体材料层的衬底，第一半导体材料层上的介电材料层，以及介电材料层上的第二层半导体材料。 晶体管的扩展沟道区域位于第二半导体材料层中，与第二半导体材料层的顶表面，侧表面和潜在部分相互作用。 栅电介质位于第二层半导体材料的顶表面和暴露的侧表面上。 栅电极位于第二半导体材料层的顶表面和暴露的侧表面上。

公开(公告)号：US20160380087A1

公开(公告)日：2016-12-29

申请号：US15258412

申请日：2016-09-07

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu

IPC: H01L29/735 ,  H01L29/08 ,  H01L21/285 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/735 ,  H01L21/28506 ,  H01L21/28518 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/42304 ,  H01L29/456 ,  H01L29/6625 ,  H01L29/66257 ,  H01L29/7317

Abstract: A bipolar transistor is supported by a substrate including a semiconductor layer overlying an insulating layer. A transistor base is formed by a base region in the semiconductor layer that is doped with a first conductivity type dopant at a first dopant concentration. The transistor emitter and collector are formed by regions doped with a second conductivity type dopant and located adjacent opposite sides of the base region. An extrinsic base includes an epitaxial semiconductor layer in contact with a top surface of the base region. The epitaxial semiconductor layer is doped with the first conductivity type dopant at a second dopant concentration greater than the first dopant concentration. Sidewall spacers on each side of the extrinsic base include an oxide liner on a side of the epitaxial semiconductor layer and the top surface of the base region.

Abstract translation: 双极晶体管由包括覆盖绝缘层的半导体层的衬底支撑。 晶体管基极由在第一掺杂浓度掺杂有第一导电型掺杂剂的半导体层中的基极区形成。 晶体管发射极和集电极由掺杂有第二导电型掺杂剂的区域形成，并且位于基极区域的相对侧。 外部基极包括与基极区域的顶表面接触的外延半导体层。 外延半导体层以大于第一掺杂剂浓度的第二掺杂剂浓度掺杂第一导电型掺杂剂。 外部基极的每一侧上的侧壁间隔物包括在外延半导体层的侧面上的氧化物衬垫和基极区域的顶表面。

公开(公告)号：US09502505B2

公开(公告)日：2016-11-22

申请号：US14587849

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Qing Liu ,  Thomas Skotnicki

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/7838 ,  H01L21/28114 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834

Abstract: An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material.

Abstract translation: 集成电路管芯包括具有第一半导体材料层的衬底，第一半导体材料层上的介电材料层，以及介电材料层上的第二层半导体材料。 晶体管的扩展沟道区域位于第二半导体材料层中，与第二半导体材料层的顶表面，侧表面和潜在部分相互作用。 栅电介质位于第二层半导体材料的顶表面和暴露的侧表面上。 栅电极位于第二半导体材料层的顶表面和暴露的侧表面上。

公开(公告)号：US20160329253A1

公开(公告)日：2016-11-10

申请号：US14705291

申请日：2015-05-06

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  Pierre Morin

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/3105 ,  H01L21/324 ,  H01L21/308 ,  H01L21/02

CPC classification number: H01L27/1211 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02592 ,  H01L21/02598 ,  H01L21/02694 ,  H01L21/3081 ,  H01L21/31051 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A tensile strained silicon layer is patterned to form a first group of fins in a first substrate area and a second group of fins in a second substrate area. The second group of fins is covered with a tensile strained material, and an anneal is performed to relax the tensile strained silicon semiconductor material in the second group of fins and produce relaxed silicon semiconductor fins in the second area. The first group of fins is covered with a mask, and silicon-germanium material is provided on the relaxed silicon semiconductor fins. Germanium from the silicon germanium material is then driven into the relaxed silicon semiconductor fins to produce compressive strained silicon-germanium semiconductor fins in the second substrate area (from which p-channel finFET devices are formed). The mask is removed to reveal tensile strained silicon semiconductor fins in the first substrate area (from which n-channel finFET devices are formed).

Abstract translation: 图案化拉伸应变硅层以在第一基板区域中形成第一组翅片，在第二基底区域中形成第二组翅片。 第二组翅片被拉伸应变材料覆盖，并且进行退火以使第二组翅片中的拉伸应变硅半导体材料松弛，并在第二区域中产生松弛的硅半导体翅片。 第一组翅片用掩模覆盖，硅 - 锗材料设置在松散的硅半导体鳍片上。 然后将来自硅锗材料的锗驱动到松散的硅半导体鳍片中，以在第二衬底区域（从其形成p沟道finFET器件）中产生压缩应变硅 - 锗半导体鳍片。 去除掩模以在第一衬底区域（从其形成n沟道finFET器件）中露出拉伸应变硅半导体鳍片。

公开(公告)号：US20160307964A1

公开(公告)日：2016-10-20

申请号：US14960595

申请日：2015-12-07

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2436 ,  H01L23/528 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1633 ,  H01L45/1691

Abstract: A resistive random access memory (RRAM) structure is formed on a supporting substrate and includes a first electrode and a second electrode. The first electrode is made of a silicided fin on the supporting substrate and a first metal liner layer covering the silicided fin. A layer of dielectric material having a configurable resistive property covers at least a portion of the first metal liner. The second electrode is made of a second metal liner layer covering the layer of dielectric material and a metal fill in contact with the second metal liner layer. A non-volatile memory cell includes the RRAM structure electrically connected between an access transistor and a bit line.

Abstract translation: 在支撑衬底上形成电阻随机存取存储器（RRAM）结构，并且包括第一电极和第二电极。 第一电极由支撑衬底上的硅化物翅片和覆盖硅化物翅片的第一金属衬垫层制成。 具有可配置电阻性能的电介质材料层覆盖第一金属衬垫的至少一部分。 第二电极由覆盖电介质材料层的第二金属衬垫层和与第二金属衬垫层接触的金属填充物制成。 非易失性存储单元包括电连接在存取晶体管和位线之间的RRAM结构。

公开(公告)号：US09461139B1

公开(公告)日：2016-10-04

申请号：US14722522

申请日：2015-05-27

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L29/10 ,  H01L21/02 ,  H01L29/735

CPC classification number: H01L29/735 ,  H01L21/28506 ,  H01L21/28518 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/42304 ,  H01L29/456 ,  H01L29/6625 ,  H01L29/66257 ,  H01L29/7317

Abstract: A bipolar transistor is supported by a substrate including a semiconductor layer overlying an insulating layer. A transistor base is formed by a base region in the semiconductor layer that is doped with a first conductivity type dopant at a first dopant concentration. The transistor emitter and collector are formed by regions doped with a second conductivity type dopant and located adjacent opposite sides of the base region. An extrinsic base includes an epitaxial semiconductor layer in contact with a top surface of the base region. The epitaxial semiconductor layer is doped with the first conductivity type dopant at a second dopant concentration greater than the first dopant concentration. Sidewall spacers on each side of the extrinsic base include an oxide liner on a side of the epitaxial semiconductor layer and the top surface of the base region.

Abstract translation: 双极晶体管由包括覆盖绝缘层的半导体层的衬底支撑。 晶体管基极由在第一掺杂浓度掺杂有第一导电型掺杂剂的半导体层中的基极区形成。 晶体管发射极和集电极由掺杂有第二导电型掺杂剂的区域形成，并且位于基极区域的相对侧。 外部基极包括与基极区域的顶表面接触的外延半导体层。 外延半导体层以大于第一掺杂剂浓度的第二掺杂剂浓度掺杂第一导电型掺杂剂。 外部基极的每一侧上的侧壁间隔物包括在外延半导体层的侧面上的氧化物衬垫和基极区域的顶表面。

公开(公告)号：US20160070060A1

公开(公告)日：2016-03-10

申请号：US14933095

申请日：2015-11-05

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu

IPC: G02B6/10 ,  G02B6/122

CPC classification number: G02B6/107 ,  C30B23/04 ,  C30B25/04 ,  C30B29/06 ,  G02B6/032 ,  G02B6/122 ,  G02B6/131 ,  G02B6/136 ,  G02B2006/12061 ,  G02B2006/12173 ,  G02B2006/12176

Abstract: A strip of sacrificial semiconductor material is formed on top of a non-sacrificial semiconductor material substrate layer. A conformal layer of the non-sacrificial semiconductor material is epitaxially grown to cover the substrate layer and the strip of sacrificial semiconductor material. An etch is performed to selectively remove the strip of sacrificial semiconductor material and leave a hollow channel surrounded by the conformal layer and the substrate layer. Using an anneal, the conformal layer and the substrate layer are reflowed to produce an optical waveguide structure including the hollow channel.

Abstract translation: 在非牺牲半导体材料衬底层的顶部上形成牺牲半导体材料条。 外延生长非牺牲半导体材料的保形层以覆盖基底层和牺牲半导体材料条。 执行蚀刻以选择性地去除牺牲半导体材料条并留下被保形层和基底层包围的中空通道。 使用退火，共形层和基底层被回流以产生包括中空通道的光波导结构。