公开(公告)号：US10109324B2

公开(公告)日：2018-10-23

申请号：US15881621

申请日：2018-01-26

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  John Eric Linstadt

IPC: G11C5/04 ,  G11C7/22 ,  G11C5/06 ,  G11C7/10

Abstract: A memory module uses dynamic data buffers for providing extended capacity for computing systems. The memory module comprises an external interface having a first set of data pins and a second set of data pins. The memory module includes a first set of memory chips and a second set of memory chips. The memory module includes a first registering clock driver to control the first set of memory chips and a second registering clock driver to control the second set of memory chips. The memory module further includes a first data buffer to connect the first set of memory chips to the first set of data pins and a second data buffer to connect the second set of memory chips to the second set of data pins.

公开(公告)号：US20180261261A1

公开(公告)日：2018-09-13

申请号：US15881621

申请日：2018-01-26

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  John Eric Linstadt

IPC: G11C5/04 ,  G11C7/22 ,  G11C7/10 ,  G11C5/06

CPC classification number: G11C5/04 ,  G11C5/063 ,  G11C7/10 ,  G11C7/22

Abstract: A memory module uses dynamic data buffers for providing extended capacity for computing systems. The memory module comprises an external interface having a first set of data pins and a second set of data pins. The memory module includes a first set of memory chips and a second set of memory chips. The memory module includes a first registering clock driver to control the first set of memory chips and a second registering clock driver to control the second set of memory chips. The memory module further includes a first data buffer to connect the first set of memory chips to the first set of data pins and a second data buffer to connect the second set of memory chips to the second set of data pins.

公开(公告)号：US10014047B2

公开(公告)日：2018-07-03

申请号：US15610001

申请日：2017-05-31

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth L. Wright

IPC: G11C7/10 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/52

CPC classification number: G11C11/4093 ,  G06F11/1048 ,  G11C7/02 ,  G11C11/4096 ,  G11C29/52 ,  G11C2029/0411

Abstract: Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable, and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.

公开(公告)号：US20180081833A1

公开(公告)日：2018-03-22

申请号：US15701698

申请日：2017-09-12

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  John Eric Linstadt ,  Catherine Chen

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.

公开(公告)号：US09875787B2

公开(公告)日：2018-01-23

申请号：US15352366

申请日：2016-11-15

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Thomas Vogelsang

IPC: G11C7/10 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4076

CPC classification number: G11C11/4093 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/4097

Abstract: A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to the data link. The buffer component is to receive signals on the second data link interface at the first voltage level. A level shifting latch produces a second voltage level in response to receiving the signals at the second data link interface, where the second voltage level is higher than the first voltage level.

公开(公告)号：US20170090533A1

公开(公告)日：2017-03-30

申请号：US15243596

申请日：2016-08-22

Applicant: RAMBUS INC.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Patrick R. Gill

IPC: G06F1/20 ,  H05K7/20

Abstract: The embodiments herein describe technologies of cryogenic digital systems with a power supply located in an ambient temperature domain and logic located in a cryogenic temperature domain. A pair of conductors is operable to carry current with a voltage difference between the power supply and the logic. The pair of conductors includes a first portion thermally coupled to a temperature-regulated or temperature-controlled intermediate temperature domain. The intermediate temperature domain is less than the ambient temperature domain and greater than the cryogenic temperature domain.

公开(公告)号：US20150248327A1

公开(公告)日：2015-09-03

申请号：US14631570

申请日：2015-02-25

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent S. Haukness ,  John Eric Linstadt ,  Scott C. Best

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1048 ,  G11C5/04 ,  G11C29/42 ,  G11C29/44 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

Abstract translation: 公开了一种存储器模块。 存储器模块包括衬底以及相应的第一，第二和第三存储器件。 第一存储器件是第一类型，其设置在衬底上并且具有可寻址的存储位置。 第二存储器件也是第一类型，并且包括专用于存储与第一存储器件中的不良存储位置相关联的故障地址信息的存储单元。 第三存储器件是第一类型的，并且包括专用于替换为存储位置不良的存储单元的存储单元。

公开(公告)号：US08880818B2

公开(公告)日：2014-11-04

申请号：US14167635

申请日：2014-01-29

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Venu Madhav Kuchibholta

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/16

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/0673 ,  G06F13/1694

Abstract: Embodiments of a memory controller are described. This memory controller includes signal connectors, which are electrically coupled to a communication path that includes multiple links, and an interface circuit, which is electrically coupled to the signal connectors. In a first operating mode, the interface circuit communicates with a first memory device via the communication path using spatial multiplexing, in which there are dedicated command/address links and dedicated data links in the communication path. Moreover, in a second operating mode, the interface circuit communicates with a second memory device via the communication path using time multiplexing, in which at least some of the links in the communication path time interleave command/address information and data.

公开(公告)号：US20140153310A1

公开(公告)日：2014-06-05

申请号：US14091213

申请日：2013-11-26

Applicant: Rambus Inc.

Inventor： Deepak Chandra Sekar ,  Brent Steven Haukness ,  John Eric Linstadt ,  Scott C. Best

IPC: G11C15/00 ,  G11C13/00

CPC classification number: G11C15/00 ,  G11C13/0002 ,  G11C15/046

Abstract: A content addressable memory can include an array of memory cells having multiple memory elements, such as RRAM elements, to store data based on a plurality resistive states. A common switching device, such as a transistor, can electrically couple a plurality of the multiple memory elements with a matchline during read, write, erase, and search operations. In search operations, the memory cells can receive a search word and selectively discharge a voltage level on the matchline based on the data stored by the memory elements and the search word provided to the memory elements. The voltage level of the matchline can indicate whether the search word matched the data stored in the memory cells. The content addressable memory can potentially have an effective memory cell sizing under 0.5F2 depending on the number of layers of memory cells formed over the switching device.

Abstract translation: 内容可寻址存储器可以包括具有多个存储器元件（诸如RRAM元件）的存储器单元阵列，以存储基于多个电阻状态的数据。 诸如晶体管的公共开关器件可以在读，写，擦除和搜索操作期间用匹配线电耦合多个多个存储器元件。 在搜索操作中，存储器单元可以接收搜索词，并且基于由存储元件存储的数据和提供给存储器元件的搜索词来选择性地排放匹配线上的电压电平。 匹配线的电压电平可以指示搜索词是否匹配存储在存储单元中的数据。 内容可寻址存储器可能潜在地具有根据在开关器件上形成的存储器单元的层数在0.5F2下的有效存储单元大小。