公开(公告)号：US11075671B2

公开(公告)日：2021-07-27

申请号：US16685861

申请日：2019-11-15

Applicant: Rambus Inc.

Inventor： John W. Poulton ,  Frederick A. Ware ,  Carl W. Werner

IPC: H04B3/56 ,  H04L25/02 ,  G06F13/40 ,  H03F3/24 ,  H04B3/54 ,  H04B10/50 ,  H04B10/40 ,  H04B10/073 ,  H04B1/04

Abstract: A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply.

公开(公告)号：US11063741B2

公开(公告)日：2021-07-13

申请号：US16659539

申请日：2019-10-21

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Jared LeVan Zerbe ,  Carl William Werner

IPC: H04L7/027 ,  H03L7/081 ,  H03L7/091 ,  H04L7/033 ,  H04L7/00

Abstract: A circuit for performing clock recovery according to a received digital signal. The circuit includes at least an edge sampler and a data sampler for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock and data clock signals offset in phase from one another to the respective clock inputs of the edge sampler and the data sampler. A digital phase detector determines if the data clock is early, late or synchronized with respect to data value transitions in the digital signal, and based on that determination provides a phase adjustment signal to the clock signal supply circuit, which is operable to vary phases of the data and edge clock signals accordingly.

公开(公告)号：US11062743B2

公开(公告)日：2021-07-13

申请号：US16802073

申请日：2020-02-26

Applicant: Rambus Inc.

Inventor： Michael L. Takefman ,  Maher Amer ,  Claus Reitlingshoefer ,  Riccardo Badalone

IPC: G11C7/00 ,  G11C7/10 ,  G11C5/04

Abstract: A system and method for providing a configurable timing control of a memory system is provided. One system has a first interface to receive a DIMM clock and configuration information, a second interface to a first data bus, and a third interface to a second data bus. The system further has flip-flops, a multiplexer coupled to the flip-flops, a first control block for controlling to hold an input data within the flip-flops, and a second control block for controlling a timing of an output data from the flip-flops via the multiplexer with a programmable delay. The input data is received via the second interface. The programmable delay is received via the first interface. The output data is sent out with the timing delay via the third interface.

公开(公告)号：US11050500B2

公开(公告)日：2021-06-29

申请号：US16552919

申请日：2019-08-27

Applicant: Rambus Inc.

Inventor： Maksym Demchenko

IPC: H04J3/06 ,  H04L29/06 ,  H04L1/00 ,  H04L12/841

Abstract: In a general aspect, a network transmission interface can include, within an egress data path, a physical coding sublayer (PCS) operating in a constant bitrate domain for transmitting data frames on a network link; a timestamp unit configured to insert timestamps in payloads of the frames; a transmission media access control (MAC) unit located at a boundary between the constant bitrate domain and a variable bitrate domain, configured to receive the frames at a variable bitrate, encapsulate the frames, and provide the encapsulated frames at a constant bitrate; a MAC layer security unit located downstream from the timestamp unit, configured to sign and optionally encrypt the payloads and expand each frame with a security tag and an integrity check value (ICV). The timestamp unit and the MAC layer security unit (26b) can both operate in the constant bitrate domain.

公开(公告)号：US11049546B2

公开(公告)日：2021-06-29

申请号：US16865928

申请日：2020-05-04

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G06F1/3237 ,  G06F1/04 ,  G06F1/3234 ,  G06F1/08 ,  G11C11/408

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

公开(公告)号：US20210193215A1

公开(公告)日：2021-06-24

申请号：US17135112

申请日：2020-12-28

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Ming Li

IPC: G11C11/4093 ,  G11C11/4096 ,  G11C5/02 ,  G11C5/04 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L23/48 ,  G11C11/406

Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

公开(公告)号：US11043258B2

公开(公告)日：2021-06-22

申请号：US16842368

申请日：2020-04-07

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Ely Tsern ,  Craig Hampel

IPC: G11C7/00 ,  G11C11/4093 ,  H01L25/065 ,  H01L25/10 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G06F13/40 ,  G06F13/16 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  H01L25/18 ,  H01L23/00

Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

公开(公告)号：US20210183434A1

公开(公告)日：2021-06-17

申请号：US17115538

申请日：2020-12-08

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness

IPC: G11C11/406 ,  G06F13/16

Abstract: The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.

公开(公告)号：US11037652B2

公开(公告)日：2021-06-15

申请号：US16870759

申请日：2020-05-08

Applicant: Rambus Inc.

Inventor： Adrian E. Ong ,  Fan Ho

IPC: G11C29/00 ,  G11C29/44 ,  G11C29/48 ,  G11C29/04 ,  G11C11/401 ,  G11C29/12 ,  G11C11/408 ,  G11C29/02

Abstract: A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.

公开(公告)号：US11036398B2

公开(公告)日：2021-06-15

申请号：US16535814

申请日：2019-08-08

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Michael Miller ,  Stephen Horn

IPC: G06F3/06 ,  G11C14/00 ,  G06F11/00 ,  G06F12/14 ,  G11C5/04 ,  G11C11/00 ,  G06F12/0802 ,  G06F13/16 ,  G11C7/10 ,  G06F11/14

Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.