公开(公告)号：US07398340B2

公开(公告)日：2008-07-08

申请号：US10182010

申请日：2001-01-26

Applicant: Myriam Chabaud ,  Thierry Albaret

Inventor： Myriam Chabaud ,  Thierry Albaret

IPC: G06F3/00 ,  G06F13/12 ,  G06F13/00 ,  G06F9/44

CPC classification number: G06F9/46

Abstract: A microprocessor-based integrated circuit for smart cards includes an application software layer and a peripheral management system including an intermediate software layer to manage the hardware processes on peripherals of the integrated circuit that are called up by at least one process of the application software layer.

Abstract translation: 用于智能卡的基于微处理器的集成电路包括应用软件层和包括中间软件层的外围管理系统，所述中间软件层管理由应用软件层的至少一个过程调用的集成电路的外围设备上的硬件过程。

公开(公告)号：US20080149936A1

公开(公告)日：2008-06-26

申请号：US11941590

申请日：2007-11-16

Applicant: SYLVAIN JOBLOT ,  Fabrice Semond ,  Jean Massies ,  Yvon Cordier ,  Jean-Yves Duboz

Inventor： SYLVAIN JOBLOT ,  Fabrice Semond ,  Jean Massies ,  Yvon Cordier ,  Jean-Yves Duboz

IPC: H01L21/763 ,  H01L31/0368

CPC classification number: H01L21/02658 ,  C30B23/025 ,  C30B23/04 ,  C30B25/04 ,  C30B25/183 ,  C30B29/406 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02664 ,  H01L27/0605 ,  H01L29/2003 ,  H01L33/007

Abstract: A process is provided for integrating a III-N component, such as GaN, on a (001) or (100) nominal silicon substrate. There are arranged a texture of elementary areas each comprising an individual surface, with the texture comprising at least one hosting area intended to receive a III-N component. A mask layer is deposited on non-hosting areas which are not intended to receive a III-N type component. The hosting area is locally prepared so as to generate on the surface of the area one domain comprising one single type of terrace. There is grown by Molecular Beam Epitaxy or Metalorganic Vapor Phase Epitaxy on the hosting area one intermediary AlN buffer layer, followed by the growth of one III-N based material so as to realize a substantially monocrystalline structure. There is eliminated the mask layer located on non-hosting areas as well as surface polycrystalline layers deposited above the mask layers, and MOS/CMOS structures are subsequent integrated on at least some of the non-hosting areas.

Abstract translation: 提供了在（001）或（100）标称硅衬底上将诸如GaN的III-N成分整合的工艺。 布置了各自包括单独表面的基本区域的纹理，其中纹理包括用于接收III-N分量的至少一个托管区域。 掩模层沉积在不意图接收III-N型组件的非托管区域上。 托管区域是本地准备的，以便在该区域的表面上生成包括一个单一类型的露台的一个域。 通过分子束外延或金属有机气相外延生长在托管区域一个中间AlN缓冲层，随后生长一种III-N基材料，以实现基本上单晶结构。 消除了位于非托管区域上的掩模层以及沉积在掩模层上方的表面多晶层，随后将MOS / CMOS结构集成在至少一些非托管区域上。

公开(公告)号：US07359640B2

公开(公告)日：2008-04-15

申请号：US10675206

申请日：2003-09-30

Applicant: Vincent Onde ,  Maxime Teissier

Inventor： Vincent Onde ,  Maxime Teissier

IPC: H04B10/00

CPC classification number: H04B10/801 ,  H04B10/2503

Abstract: Optical coupling device operates over a bidirectional data link between at least first and second communicators, each communicating data along a common wire of the data link. The device includes at least first and second optical couplers, each including a photon flux source and a photon flux detector. The photon flux source of the first and second optical couplers, respectively, is commanded by the first and second communicator, respectively. The photon flux detector of the first and second optical coupler, respectively, produces a signal on the data link at the first and second communicator, respectively, in response to the photon flux source of the second and first optical coupler, respectively, from the second and first communicator, respectively. An inhibitor inhibits the photon flux source of the second and first optical coupler, respectively, in response to an activation of the photon flux source of the first and second optical coupler, respectively.

Abstract translation: 光耦合装置通过至少第一和第二通信器之间的双向数据链路进行操作，每个通信器沿着数据链路的公共线传送数据。 该装置包括至少第一和第二光耦合器，每个光耦合器包括光子通量源和光子通量检测器。 第一和第二光耦合器的光子通量分别由第一和第二通信器命令。 第一和第二光耦合器的光子通量检测器分别响应于来自第二和第二光耦合器的第二和第二光耦合器的光子通量源分别在第一和第二通信器处的数据链路上产生信号 和第一传播者。 响应于第一和第二光耦合器的光子通量源的激活，抑制剂分别抑制第二和第一光耦合器的光子通量源。

公开(公告)号：US20080076211A1

公开(公告)日：2008-03-27

申请号：US11904859

申请日：2007-09-27

Applicant: Fabrice Casset ,  Cedric Durand ,  Pascal Ancey

Inventor： Fabrice Casset ,  Cedric Durand ,  Pascal Ancey

IPC: H01L21/56

CPC classification number: B81C1/0065 ,  B81B2201/0271 ,  B81B2207/015 ,  H03H3/0073 ,  H03H9/1057 ,  H03H9/2405 ,  H03H2009/02496

Abstract: Method for making an electromechanical component on a plane substrate and comprising at least one structure vibrating in the plane of the substrate and actuation electrodes. The method comprises at least the following steps in sequence: formation of the substrate comprising one silicon area partly covered by two insulating areas, formation of a sacrificial silicon and germanium alloy layer by selective epitaxy starting from the uncovered part of the silicon area, formation of a strongly doped silicon layer by epitaxy, comprising a monocrystalline area arranged on said sacrificial layer and two polycrystalline areas arranged on insulating areas, simultaneous formation of the vibrating structure and actuation electrodes, by etching of a predetermined pattern in the monocrystalline area designed to form spaces between the electrodes and the vibrating structure, elimination of said sacrificial silicon and germanium alloy layer by selective etching.

Abstract translation: 一种用于在平面基板上制造机电部件并且包括在所述基板和致动电极的平面中振动的至少一个结构的方法。 该方法至少包括以下步骤：基底的形成，其包括由两个绝缘区域部分覆盖的一个硅区域，通过从硅区域的未覆盖部分开始的选择性外延形成牺牲硅和锗合金层，形成 通过外延的强掺杂硅层，包括布置在所述牺牲层上的单晶区域和布置在绝缘区域上的两个多晶区域，同时形成振动结构和致动电极，通过在设计成形成空间的单晶区域中蚀刻预定图案 在电极和振动结构之间，通过选择性蚀刻消除所述牺牲硅和锗合金层。

公开(公告)号：US20080062806A1

公开(公告)日：2008-03-13

申请号：US11850510

申请日：2007-09-05

Applicant: Christophe Rodat ,  Thierry Giovinazzi

Inventor： Christophe Rodat ,  Thierry Giovinazzi

IPC: G11C8/12

CPC classification number: G11C7/12 ,  G11C7/1048 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2207/002 ,  G11C2213/79

Abstract: An integrated circuit includes a non-volatile memory having memory cells, a memory cell selection circuit having selection blocks, a first device supplying a first voltage applicable to memory cells, a second device supplying a second voltage applicable to memory cells. Each memory cell selection block includes a first selection sub-block to link the memory cell to the first device and a second selection sub-block to link the memory cell to the second device. The first sub-block includes MOS transistors of a first type of conductivity, and the second sub-block includes MOS transistors of a second type of conductivity. Application may be particularly but not exclusively to phase change memories.

Abstract translation: 集成电路包括具有存储单元的非易失性存储器，具有选择块的存储单元选择电路，提供适用于存储单元的第一电压的第一器件，提供适用于存储器单元的第二电压的第二器件。 每个存储器单元选择块包括用于将存储器单元链接到第一设备的第一选择子块和将存储器单元链接到第二设备的第二选择子块。 第一子块包括具有第一类导电性的MOS晶体管，第二子块包括第二导电类型的MOS晶体管。 应用可以特别地但不是排他地用于相变存储器。

公开(公告)号：US20080061835A1

公开(公告)日：2008-03-13

申请号：US11900622

申请日：2007-09-11

Applicant: Riccardo Locatelli ,  Marcello Coppola ,  Daniele Mangano ,  Luca Fanucci ,  Franscesco Vitullo ,  Dario Zandri ,  Nicola L'Insalata

Inventor： Riccardo Locatelli ,  Marcello Coppola ,  Daniele Mangano ,  Luca Fanucci ,  Franscesco Vitullo ,  Dario Zandri ,  Nicola L'Insalata

IPC: H03L7/00

CPC classification number: H04L7/0012 ,  H04L7/0045 ,  H04L7/02

Abstract: A synchronization system to synchronize modules (TX, RX) in an integrated circuit, such as a VLSI integrated circuit, in which the modules receive respective first and second clock signals (TX_CLK, RX_CLK) having a same frequency but being shifted by a constant and unknown phase difference. The system includes a first latch means for latching and delivering data in synchronism with the first clock signal and second latch means for latching data issued from the first latch means and delivering data in synchronism with the second clock signal, first and second latch means being controlled by first and second control signals (strobe_W, strobe_R) elaborated respectively from said first and second clock signals and one of said first and second control signal being shifted by an amount corresponding at least to the set-up time of at least one of said first and second latch means.

Abstract translation: 一种同步系统，用于在诸如VLSI集成电路的集成电路中同步模块（TX，RX），其中模块接收具有相同频率但被偏移常数的相应的第一和第二时钟信号（TX_CLK，RX_CLK） 未知相位差。 该系统包括用于与第一时钟信号同步地锁存和传送数据的第一锁存装置和用于锁存从第一锁存装置发出的数据并与第二时钟信号同步传送数据的第二锁存装置，第一和第二锁存装置被控制 通过分别从所述第一和第二时钟信号详细阐述的第一和第二控制信号（strobe_W，strobe_R），并且所述第一和第二控制信号中的一个被移位至少与所述第一和第二时钟信号中的至少一个的建立时间相对应的量 和第二锁定装置。

公开(公告)号：US20080049524A1

公开(公告)日：2008-02-28

申请号：US11844025

申请日：2007-08-23

Applicant: Gilles Gasiot ,  Francois Jacquet ,  Philippe Roche

Inventor： Gilles Gasiot ,  Francois Jacquet ,  Philippe Roche

IPC: G11C7/00

CPC classification number: G11C11/4125

Abstract: A memory cell stores information in the form of a first logic level and a second logic level that are complementary to each other. The memory cell includes a first storage circuit and a second storage circuit for storing the first logic level and the second logic level. The first and second storage circuits each have a respective input and output. An isolation circuit provides electrical isolation of the input of the first storage device from the output of the second storage device, except during access to the first and second storage circuits.

Abstract translation: 存储器单元以彼此互补的第一逻辑电平和第二逻辑电平的形式存储信息。 存储单元包括用于存储第一逻辑电平和第二逻辑电平的第一存储电路和第二存储电路。 第一和第二存储电路各自具有相应的输入和输出。 除了在访问第一和第二存储电路期间，隔离电路提供第一存储装置的输入与第二存储装置的输出的电隔离。

公开(公告)号：US20080048804A1

公开(公告)日：2008-02-28

申请号：US11845268

申请日：2007-08-27

Applicant: Alexandre Volatier ,  Pascal Ancey ,  Bertrand Dubus

Inventor： Alexandre Volatier ,  Pascal Ancey ,  Bertrand Dubus

IPC: H03H9/56 ,  H01L41/22

CPC classification number: H03H9/02228 ,  Y10T29/42

Abstract: A coupled Lamb wave resonator filter includes first and second Lamb wave resonators. The first Lamb wave resonator includes a first resonant layer, and first and second electrodes on opposite sides of the first resonant layer. The second Lamb wave resonator includes a second resonant layer, and third and fourth electrodes on opposite sides of the second resonant layer. One of the sides of the first resonant layer belongs to a plane parallel to a plane corresponding to one of the sides of the second resonant layer. Both planes pass through the third and fourth electrodes of the second Lamb wave resonator. A periodic lattice acoustically couples the first and second resonant layers.

Abstract translation: 耦合兰姆波谐振滤波器包括第一和第二兰姆波谐振器。 第一兰姆波谐振器包括第一谐振层，以及在第一谐振层的相对侧上的第一和第二电极。 第二兰姆波谐振器包括第二谐振层，第二谐振层的相对侧上的第三和第四电极。 第一共振层的一个侧面属于平行于与第二共振层的一个侧面相对应的平面的平面。 两个平面通过第二兰姆波谐振器的第三和第四电极。 周期性晶格声耦合第一和第二谐振层。

公开(公告)号：US20080024244A1

公开(公告)日：2008-01-31

申请号：US11829549

申请日：2007-07-27

Applicant: Andrea Cathelin ,  Stephane Razafimandiby ,  Andreas Kaiser

Inventor： Andrea Cathelin ,  Stephane Razafimandiby ,  Andreas Kaiser

IPC: H03H9/00

CPC classification number: H03H9/0095 ,  H03H2009/02204

Abstract: A filtering circuit based on a lattice structure comprising a first and a second input and a first and second output. The circuit further comprises two series impedance and two parallel impedance which each comprises an acoustic resonator associated with two inductive and capacitive components which can be adjusted by a first control value. The second and fourth impedance comprise each an acoustic resonator associated to two inductive and capacitive components which are adjustable by means of a second control value. A control circuit generates the two control values which simultaneously comprise a common mode potential and a differential mode potential which allows the emergence of first and second pass bands which are usable for realizing two different bandpass filters.

Abstract translation: 一种基于包括第一和第二输入以及第一和第二输出的晶格结构的滤波电路。 电路还包括两个串联阻抗和两个并联阻抗，每个阻抗均包括与两个电感和电容部件相关联的声谐振器，这两个电感和电容部件可以通过第一控制值进行调节。 第二和第四阻抗包括每个与谐振器相关联的声谐振器，两个电感和电容元件可通过第二控制值进行调节。 控制电路产生同时包括共模电位和差模电位的两个控制值，允许出现可用于实现两个不同带通滤波器的第一和第二通带。

公开(公告)号：US20080022174A1

公开(公告)日：2008-01-24

申请号：US11774344

申请日：2007-07-06

Applicant: Frederic Bancel ,  David Hely

Inventor： Frederic Bancel ,  David Hely

IPC: G01R31/28

CPC classification number: G01R31/318555 ,  G01R31/31719

Abstract: An electronic circuit includes configurable cells each having a test input and an output. The configurable cells are connected to one another in a chain in a predefined order via their test input and their output to form a test register based on receiving a chaining command signal. The electronic circuit also includes a detection circuit activated by the chaining command signal to produce a state signal representing a state of initialization of a first set of configurable cells A multiplexing circuit selectively connects the test input of each configurable cell to a second set of the configurable cells either to the output of a preceding configurable cell or to an output of a decoy data generator based on the state signal.

Abstract translation: 电子电路包括每个具有测试输入和输出的可配置单元。 可配置单元通过其测试输入及其输出以预定义的顺序彼此连接，以形成基于接收链接命令信号的测试寄存器。 电子电路还包括由链接命令信号激活的检测电路，以产生表示第一组可配置单元的初始化状态的状态信号。复用电路选择性地将每个可配置单元的测试输入连接到第二组可配置单元 基于状态信号，将信元发送到前一个可配置信元的输出或诱饵数据发生器的输出端。