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公开(公告)号：US12216541B2
公开(公告)日：2025-02-04
申请号：US18406894
申请日：2024-01-08
Applicant: Micron Technology, Inc.
Inventor： Sanjay Subbarao
IPC: H04L1/00 , G06F11/07 , G06F11/10 , G06F11/14 , H03M13/00 , H03M13/11 , H03M13/13 , H04L1/18 , H04L1/1812 , H04L1/1867
Abstract: Various embodiments provide block failure protection for a memory sub-system that supports zones, such a memory sub-system that uses a RAIN (redundant array of independent NAND-type flash memory devices) technique for data error-correction. For some embodiments, non-parity zones of a memory sub-system that are filling up at a similar rate are matched together, a parity is generated for stored data from across the matching zones, and the generated parity is stored in a parity zone of the memory device.
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公开(公告)号：US12216525B2
公开(公告)日：2025-02-04
申请号：US18137895
申请日：2023-04-21
Applicant: Micron Technology, Inc.
Inventor： Luca Porzio , Alessandro Orlando , Danilo Caraccio , Roberto Izzi
Abstract: Methods, systems, and devices for detecting page fault traffic are described. A memory device may execute a self-learning algorithm to determine a priority size for read requests, such as a maximum readahead window size or other size related to page faults in a memory system. The memory device may determine the priority size based at least in part on by tracking how many read requests are received for different sizes of sets of data. Once the priority size is determined, the memory device may detect subsequent read requests for sets of data having the priority size, and the memory device may prioritize or other optimize the execution of such read requests.
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公开(公告)号：US12216521B2
公开(公告)日：2025-02-04
申请号：US17887268
申请日：2022-08-12
Applicant: Micron Technology, Inc.
Inventor： Rakeshkumar Dayabhai Vaghasiya
Abstract: Methods, systems, and devices for a common error protection buffer for multiple cursors are described. A memory device may receive a command to write data to a memory system. The memory device may assign portions of the data to respective pages of a first cursor and generate error protection data for the assigned data. The memory device may assign the generated error protection data to an error protection buffer common to multiple cursors, for example, by performing an combination operation. The memory device may increment a counter associated with the error protection buffer. The memory device may write a summary of contents of the error protection buffer and a position of each cursor related to the error protection data based on the counter satisfying a threshold. The memory device may perform a readback operation to facilitate garbage collection without losing error protection data.
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公开(公告)号：US20250040439A1
公开(公告)日：2025-01-30
申请号：US18917686
申请日：2024-10-16
Applicant: Micron Technology, Inc.
Inventor： Anthony D. Veches
Abstract: A memory device comprises multiple memory dice arranged vertically in a stack of memory dice and at least one thermoelectric die contacting the bulk silicon layer of at least one of the memory dice of the multiple memory dice. Each memory die of the multiple memory dice includes an active circuitry layer that includes memory cells of a memory array and a bulk silicon layer. The thermoelectric die is configured to one or both of reduce heat from the memory die when a current is applied to terminals of the thermoelectric die and generate a voltage at the terminals of the thermoelectric die when heat from the memory die is applied to the thermoelectric die.
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公开(公告)号：US20250040121A1
公开(公告)日：2025-01-30
申请号：US18777208
申请日：2024-07-18
Applicant: Micron Technology, Inc.
Inventor： Yuanzhi Ma , Scott E. Sills , Si-Woo Lee , David K. Hwang , Yoshitaka Nakamura , Yuichi Yokoyama , Pavani Vamsi Krishna Nittala , Glen H. Walters , Gautham Muthusamy , Haitao Liu , Kamal Karda
Abstract: Methods, systems, and devices for multi-layer capacitors for three-dimensional memory systems are described. Memory cells of a memory system may include capacitors having dielectric material between multiple interfaces (e.g., concentric interfaces) of a bottom electrode and a top electrode. A bottom electrode may include a first portion wrapping around a portion of a semiconductor material that is contiguous with a channel of a transistor, and a top electrode may include a first portion wrapping around the first portion of the bottom electrode. The bottom electrode may also include a second portion wrapping around the first portion of the top electrode, and the top electrode may also include a second portion wrapping around the second portion of the bottom electrode. The dielectric material may include respective portions between each interface of the bottom electrode and top electrode which, in some examples, may be a contiguous implementation of the dielectric material.
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Patent Agency Ranking
公开(公告)号：US20250038965A1
公开(公告)日：2025-01-30
申请号：US18912464
申请日：2024-10-10
Applicant: Micron Technology, Inc.
Inventor： Antonino Mondello , Alberto Troia
Abstract: Disclosed are techniques for remotely managing computing devices using blockchain and DICE-RIoT. In one embodiment, a method is disclosed comprising scanning a network to obtain a list of devices on the network; classifying the devices as either controlled or uncontrolled devices; establishing a secure channel with the controlled devices; issuing one or more control commands to the controlled devices over the secure channel, the one or more control commands included within a signed message, the signed message signed using a private key of the sender and verified using a public key of the receiver, the private key and public key generated during the establishing of the secure channel; receiving a response to the control commands; and logging the control commands and the response in a blockchain.
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公开(公告)号：US20250036579A1
公开(公告)日：2025-01-30
申请号：US18625212
申请日：2024-04-03
Applicant: Micron Technology, Inc.
Inventor： Raymond Chang , Raghukiran Sreeramaneni , Nevil N. Gajera
Abstract: A memory device (e.g., a high-bandwidth memory (HBM) device) with multiple physical interfaces (PHYs) is disclosed. The memory device includes a base semiconductor die having a first physical interface (PHY) arranged in accordance with a Joint Electron Device Engineering Council (JEDEC) standard and a second PHY arranged differently from the first PHY and electrically disconnected from the first PHY. The base semiconductor die further includes first contacts disposed at a first side of the base semiconductor die and second contacts disposed at a second side of the base semiconductor die opposite the first side. The first contacts and the second contacts couple with a first one of the first PHY and the second PHY. The memory device further includes one or more memory dies coupled with the base semiconductor die through the second contacts.
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公开(公告)号：US20250036303A1
公开(公告)日：2025-01-30
申请号：US18784167
申请日：2024-07-25
Applicant: Micron Technology, Inc.
Inventor： Kevin R. Brandt , Sampath Ratnam , David Ebsen , Brent Carl Byron , Daniel J. Hubbard
IPC: G06F3/06
Abstract: Aspects of the present disclosure configure a memory sub-system controller to allow a host to control storage on the memory sub-system based on endurance of memory components. The controller groups the set of memory components into a plurality of categories representing different endurance levels of the set of memory components and communicates, to a host, information about the plurality of categories. The controller receives, from the host, a request to program data into an individual memory component of the set of memory components, the request being generated by the host based on a type of the data and an individual category associated with the individual memory component.
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公开(公告)号：US12213325B2
公开(公告)日：2025-01-28
申请号：US17499709
申请日：2021-10-12
Applicant: Micron Technology, Inc.
Inventor： Anna Maria Conti , Andrea Gotti , Pavan Reddy K. Aella
Abstract: Methods, systems, and devices for techniques for manufacturing a double electrode memory array are described. A memory device may be fabricated using a sequence of fabrication steps that include depositing a first stack of materials including a conductive layer, an interface layer, and a first electrode layer. The first stack of materials may be etched to form a first set of trenches. A second stack of materials may be deposited on top of the first stack of materials. The second stack may include a second electrode layer in contact with the first electrode layer, a storage layer, and a third electrode layer. The second stack of materials may be etched to form a second set of trenches above the first set of trenches, and filled with a sealing layer and a dielectric material. The sealing layer may not extend substantially into the first set of trenches.
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公开(公告)号：US12213321B2
公开(公告)日：2025-01-28
申请号：US17515065
申请日：2021-10-29
Applicant: Micron Technology, Inc.
Inventor： Kamal M. Karda , Richard E. Fackenthal , Durai Vishak Nirmal Ramaswamy
Abstract: Some embodiments include apparatuses and methods forming the apparatuses. One of the apparatuses includes a first memory cell including a first transistor including a first channel region and a first charge storage structure, and a second transistor including a second channel region formed over the charge storage structure; a second memory cell adjacent the first memory cell, the second memory cell including a third transistor including a third channel region and a second charge storage structure, and a fourth transistor including a fourth channel region formed over the second charge storage structure; a first access line adjacent a side of the first memory cell; a second access line adjacent a side of the second memory cell; a first dielectric material adjacent the first channel region; a second dielectric material adjacent the third channel region; and a conductive structure between the first and second dielectric materials and adjacent the first and second dielectric materials.
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