公开(公告)号：US11730433B2

公开(公告)日：2023-08-22

申请号：US17529543

申请日：2021-11-18

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Gilles Gasiot ,  Severin Trochut ,  Olivier Le Neel ,  Victor Malherbe

IPC: A61B6/00 ,  G01T1/24

CPC classification number: A61B6/4208 ,  G01T1/24

Abstract: An X-ray detector includes a first circuit with an NPN-type bipolar transistor and a second circuit configured to compare a voltage at a terminal of the NPN-type bipolar transistor with a reference value substantially equal to a value of the terminal voltage which would occur when the first circuit has been exposed to a threshold quantity of X-rays.

公开(公告)号：US11723220B2

公开(公告)日：2023-08-08

申请号：US17244514

申请日：2021-04-29

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Remy Berthelon ,  Olivier Weber

IPC: H10B63/00

CPC classification number: H10B63/32 ,  H10B63/80

Abstract: A method for manufacturing an electronic chip includes providing a semiconductor layer located on an insulator covering a semiconductor substrate. First and second portions of the semiconductor layer are oxidized up to the insulator. Stresses are generated in third portions of the semiconductor layer, and each of the third portions extend between two portions of the semiconductor layer that are oxidized. Cavities are formed which extend at least to the substrate through the second portions and the insulator. Bipolar transistors are formed in at least part of the cavities and first field effect transistors are formed in and on the third portions. Phase change memory points are coupled to the bipolar transistors.

公开(公告)号：US11709315B2

公开(公告)日：2023-07-25

申请号：US17540626

申请日：2021-12-02

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Frederic Boeuf ,  Charles Baudot

IPC: G02B6/12 ,  G02B6/30 ,  G02B6/124 ,  G02B6/122 ,  G02B6/126 ,  G02B6/27 ,  G02B6/34 ,  G02B6/42

CPC classification number: G02B6/12002 ,  G02B6/122 ,  G02B6/124 ,  G02B6/12004 ,  G02B6/126 ,  G02B6/2773 ,  G02B6/30 ,  G02B6/34 ,  G02B6/4204 ,  G02B2006/12104 ,  G02B2006/12107 ,  G02B2006/12116 ,  G02B2006/12147

Abstract: A three-dimensional photonic integrated structure includes a first semiconductor substrate and a second semiconductor substrate. The first substrate incorporates a first waveguide and the second semiconductor substrate incorporates a second waveguide. An intermediate region located between the two substrates is formed by a one dielectric layer. The second substrate further includes an optical coupler configured for receiving a light signal. The first substrate and dielectric layer form a reflective element located below and opposite the grating coupler in order to reflect at least one part of the light signal.

公开(公告)号：US11695028B2

公开(公告)日：2023-07-04

申请号：US17514953

申请日：2021-10-29

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy ,  Stephane Hulot ,  Andrej Suler ,  Nicolas Virollet

IPC: H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/1461 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14612 ,  H01L27/14636 ,  H01L27/14621 ,  H01L27/14627

Abstract: A semiconductor image sensor includes a plurality of pixels. Each pixel of the sensor includes a semiconductor substrate having opposite front and back sides and laterally delimited by a first insulating wall including a first conductive core insulated from the substrate, electron-hole pairs being capable of forming in the substrate due to a back-side illumination. A circuit is configured to maintain, during a first phase in a first operating mode, the first conductive core at a first potential and to maintain, during at least a portion of the first phase in a second operating mode, the first conductive core at a second potential different from the first potential.

公开(公告)号：US11690303B2

公开(公告)日：2023-06-27

申请号：US17216193

申请日：2021-03-29

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Remy Berthelon ,  Franck Arnaud

IPC: G11C11/00 ,  H10N70/20 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/231 ,  H10B63/00 ,  H10N70/021 ,  H10N70/063 ,  H10N70/8828

Abstract: An electronic chip includes at least a first array of first elementary cells and a second array of second elementary cells. The first and second elementary cells form two types of phase change memory having a storage element formed by a volume of phase change material having either a crystalline state or an amorphous state depending on the bit stored. Each first elementary cell includes a volume of a first phase change material, and each second elementary cell includes a volume of a second phase change material that is different from the first material. Each elementary cell includes a heating connector configured for the passage of a heating current adapted to cause a phase change of the volume of phase change material of the elementary cell.

公开(公告)号：US11682689B2

公开(公告)日：2023-06-20

申请号：US17128604

申请日：2020-12-21

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy ,  Sonarith Chhun

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L27/14632 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/1464

Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.

公开(公告)号：US20230178677A1

公开(公告)日：2023-06-08

申请号：US18147566

申请日：2022-12-28

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Younes BENHAMMOU ,  Dominique GOLANSKI ,  Denis RIDEAU

IPC: H01L31/107 ,  H01L31/028 ,  H01L31/0745 ,  H01L31/18

CPC classification number: H01L31/107 ,  H01L31/0284 ,  H01L31/0745 ,  H01L31/1812

Abstract: The present disclosure relates to a photodiode comprising a first part made of silicon and a second part made of doped germanium lying on and in contact with the first part, the first part comprising a stack of a first area and of a second area forming a p-n junction and the doping level of the germanium increasing as the distance from the p-n junction increases.

公开(公告)号：US20230090291A1

公开(公告)日：2023-03-23

申请号：US17992602

申请日：2022-11-22

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean JIMENEZ MARTINEZ

IPC: H01L21/8228 ,  H01L27/082

Abstract: A microelectronic device includes a PNP transistor and NPN transistor arranged vertically in a P-type doped semiconductor substrate. The PNP and NPN transistors are manufactured by: forming an N+ doped isolating well for the PNP transistor in the semiconductor substrate; forming a P+ doped region in the N+ doped isolating well; epitaxially growing a first semiconductor layer on the semiconductor substrate; forming an N+ doped well for the NPN transistor, where at least part of the N+ doped well extends into the first semiconductor layer; then epitaxially growing a second semiconductor layer on the first semiconductor layer; forming a P doped region forming the collector of the PNP transistor in the second semiconductor layer and in electrical contact with the P+ doped region; and forming an N doped region forming the collector of the NPN transistor in the second semiconductor layer and in electrical contact with the N+ doped well.

公开(公告)号：US20230051181A1

公开(公告)日：2023-02-16

申请号：US17883764

申请日：2022-08-09

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Frederic LALANNE ,  Pierre MALINGE

IPC: H04N5/343 ,  G01J1/44 ,  H04N5/3745 ,  H04N5/378 ,  H04N5/33

Abstract: A photosensitive sensor is capable of operating in a global shutter mode and in a rolling shutter mode. The sensor includes at least one pixel with a photosensitive region configured to photogenerate charges. A first transfer gate is configured to transfer photogenerated charges from the photosensitive region to a transfer node. A source-follower transistor is configured to transmit a reading signal to a read node, in the global shutter mode, in a manner controlled by a potential of the photogenerated charges on the transfer node. A second transfer gate is configured to transfer the photogenerated charges from the photosensitive region to the read node in the rolling shutter mode.

公开(公告)号：US11581345B2

公开(公告)日：2023-02-14

申请号：US17122314

申请日：2020-12-15

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H04N5/3745 ,  H01L27/146

Abstract: An image sensor includes a pixel with a photosensitive region accommodated within a semiconductor substrate and a MOS capacitive element with a conducting electrode electrically isolated by a dielectric layer. The dielectric layer forms an interface with both the photosensitive region and the semiconductor substrate, the interface of the dielectric layer including charge traps. A control circuit biases the electrode of the MOS capacitive element with a charge pumping signal designed to generate an alternation of successive inversion regimes and accumulation regimes in the photosensitive region. The charge pumping signal produces recombinations of photogenerated charges in the charge traps of the interface of the dielectric layer and the generation of a substrate current to empty recombined photogenerated charges.