公开(公告)号：US08095887B2

公开(公告)日：2012-01-10

申请号：US11496536

申请日：2006-08-01

Applicant: Jong-ho Lee ,  Kwang-kee Lee ,  Un-gyo Jung ,  Glenn A. Adams

Inventor： Jong-ho Lee ,  Kwang-kee Lee ,  Un-gyo Jung ,  Glenn A. Adams

IPC: G06F3/048

CPC classification number: G09G5/14 ,  G09G2340/0407 ,  G09G2340/0464 ,  G09G2340/10 ,  G09G2340/12 ,  G09G2340/125 ,  H04N5/445 ,  H04N5/44591 ,  H04N5/45 ,  H04N21/4312 ,  H04N21/4314 ,  H04N21/4316 ,  H04N21/443 ,  H04N21/4622

Abstract: An apparatus for providing multiple screens and a method of dynamically configuring multiple screens are provided. The apparatus for providing multiple screens includes a service processing module which generates logical screens displaying services and a display screen and swaps the services between the logical screens, and an output module which maps the logical screens to arbitrary locations on the display screen.

Abstract translation: 提供了一种用于提供多个屏幕的装置和一种动态配置多个屏幕的方法。 用于提供多个屏幕的装置包括产生显示服务的逻辑屏幕和显示屏幕并交换逻辑屏幕之间的服务的服务处理模块以及将逻辑屏幕映射到显示屏幕上的任意位置的输出模块。

公开(公告)号：US20120003565A1

公开(公告)日：2012-01-05

申请号：US13256769

申请日：2010-03-16

Applicant: Ji-Won Son ,  Ho-Sung Noh ,  Hae-Weon Lee ,  Jong Ho Lee ,  Hae-Ryoung Kim ,  Jong Cheol Kim

Inventor： Ji-Won Son ,  Ho-Sung Noh ,  Hae-Weon Lee ,  Jong Ho Lee ,  Hae-Ryoung Kim ,  Jong Cheol Kim

IPC: H01M4/86 ,  H01M8/00 ,  C23C16/48 ,  B05D1/04 ,  B05D3/02 ,  H01M8/10 ,  C23C14/34 ,  B82Y30/00

CPC classification number: H01M8/1206 ,  H01M4/861 ,  H01M8/1231 ,  Y02E60/521 ,  Y02E60/525 ,  Y02P70/56

Abstract: The present invention relates to a solid oxide fuel cell having a gradient structure in which pore size becomes gradually smaller from a porous electrode to an electrolyte thin film in order to form a dense electrolyte thin film of less than about 2 microns and preferably less than 1 micron on the porous electrode.

Abstract translation: 本发明涉及具有梯度结构的固体氧化物燃料电池，其中孔径从多孔电极逐渐变小至电解质薄膜，以形成小于约2微米，优选小于1的致密电解质薄膜 微米在多孔电极上。

公开(公告)号：US08039355B2

公开(公告)日：2011-10-18

申请号：US12632115

申请日：2009-12-07

Applicant: Jong-Ho Lee

Inventor： Jong-Ho Lee

IPC: H01L21/20

CPC classification number: H01L27/0629 ,  H01L27/0682 ,  H01L28/20 ,  H01L28/40

Abstract: A PIP capacitor and methods thereof. A method of fabricating a PIP capacitor may include forming a field oxide film over a silicon substrate to define a device isolating region and/or an active region. A method of fabricating a PIP capacitor may include forming a lower polysilicon electrode having doped impurities on and/or over an field oxide film. A method of fabricating a PIP capacitor may include performing an oxidizing step to form a first oxide film over a polysilicon and/or a second oxide film on and/or over an active region. A method of fabricating a PIP capacitor may include forming an upper polysilicon electrode on and/or over a region of a first oxide film and forming a gate electrode on and/or over a second oxide film at substantially the same time. A method of fabricating a PIP capacitor may include forming a polysilicon resistor. A PIP capacitor is disclosed.

Abstract translation: 一种PIP电容器及其方法。 制造PIP电容器的方法可以包括在硅衬底上形成场氧化物膜以限定器件隔离区和/或有源区。 制造PIP电容器的方法可以包括在场氧化物膜上形成具有掺杂杂质的下部多晶硅电极。 制造PIP电容器的方法可以包括执行氧化步骤以在活性区上和/或上方在多晶硅和/或第二氧化物膜上形成第一氧化膜。 制造PIP电容器的方法可以包括在第一氧化物膜的区域上和/或上方形成上部多晶硅电极，并且在基本上同时在第二氧化膜上形成和/或在第二氧化物膜上形成栅电极。 制造PIP电容器的方法可以包括形成多晶硅电阻器。 公开了一种PIP电容器。

公开(公告)号：US20110198710A1

公开(公告)日：2011-08-18

申请号：US13039811

申请日：2011-03-03

Applicant: Jong-Ho LEE ,  Nae-In LEE

Inventor： Jong-Ho LEE ,  Nae-In LEE

IPC: H01L29/772 ,  H01L29/06

CPC classification number: H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7881 ,  H01L29/94

Abstract: A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides.

Abstract translation: 半导体器件包括硅酸盐界面层和覆盖硅酸盐界面层的高k电介质层。 高k电介质层包括金属合金氧化物。

公开(公告)号：US20110198687A1

公开(公告)日：2011-08-18

申请号：US13123458

申请日：2009-09-24

Applicant: Jong-Ho Lee

Inventor： Jong-Ho Lee

IPC: H01L27/105 ,  H01L29/792

CPC classification number: H01L27/1021 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11556

Abstract: Provided a flash memory cell stack, a flash memory cell stack string, a cell stack array, and a method of fabricating thereof. A flash memory cell stack includes a semiconductor substrate; a control electrode provided in a vertical pillar shape on a surface of the semiconductor substrate; an insulating film provided between the control electrode and the semiconductor substrate; a gate stack provided on a side surface of the control electrode; a plurality of first insulating films provided as layers on a side surface of the gate stack; a plurality of second doping semiconductor areas provided as layers on a side surface of the gate stack; and a first doping semiconductor area provided on side surfaces of the first insulating films and the second doping semiconductor areas, wherein the first insulating films and the second doping semiconductor areas are alternately provided as layers on the side surface of the gate stack.

Abstract translation: 提供了闪存单元堆叠，闪存单元堆栈串，单元堆栈阵列及其制造方法。 闪存单元堆叠包括半导体衬底; 在半导体衬底的表面上设置成垂直柱状的控制电极; 设置在所述控制电极和所述半导体基板之间的绝缘膜; 设置在所述控制电极的侧面上的栅极堆叠; 多个第一绝缘膜，其设置在所述栅极堆叠的侧表面上的层; 多个第二掺杂半导体区域，其设置在栅叠层的侧表面上; 以及设置在所述第一绝缘膜和所述第二掺杂半导体区域的侧表面上的第一掺杂半导体区域，其中所述第一绝缘膜和所述第二掺杂半导体区域在所述栅极堆叠的侧表面上交替地设置为层。

公开(公告)号：US07952118B2

公开(公告)日：2011-05-31

申请号：US11946153

申请日：2007-11-28

Applicant: Hyung-suk Jung ,  Jong-ho Lee ,  Sung-kee Han ,  Ha-jin Lim

Inventor： Hyung-suk Jung ,  Jong-ho Lee ,  Sung-kee Han ,  Ha-jin Lim

IPC: H01L29/78

CPC classification number: H01L21/02178 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/02362 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/3142 ,  H01L21/31645 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A semiconductor includes a channel region in a semiconductor substrate, a gate dielectric film on the channel region, and a gate on the gate dielectric film. The gate includes a doped metal nitride film, formed from a nitride of a first metal and doped with a second metal which is different from the first metal, and a conductive polysilicon layer formed on the doped metal nitride film. The gate may further include a metal containing capping layer interposed between the doped metal nitride film and the conductive polysilicon layer.

Abstract translation: 半导体包括半导体衬底中的沟道区域，沟道区上的栅极电介质膜和栅极电介质膜上的栅极。 栅极包括由第一金属的氮化物形成并掺杂有与第一金属不同的第二金属的掺杂金属氮化物膜和形成在掺杂金属氮化物膜上的导电多晶硅层。 栅极还可以包括插入在掺杂的金属氮化物膜和导电多晶硅层之间的含金属的覆盖层。

公开(公告)号：US07902019B2

公开(公告)日：2011-03-08

申请号：US12098373

申请日：2008-04-04

Applicant: Jong-Ho Lee ,  Nae-In Lee

Inventor： Jong-Ho Lee ,  Nae-In Lee

IPC: H01L21/8249

CPC classification number: H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7881 ,  H01L29/94

Abstract: A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides.

Abstract translation: 半导体器件包括硅酸盐界面层和覆盖硅酸盐界面层的高k电介质层。 高k电介质层包括金属合金氧化物。

公开(公告)号：US07888785B2

公开(公告)日：2011-02-15

申请号：US12219263

申请日：2008-07-18

Applicant: Eun-Chul Ahn ,  Min-Ho O ,  Jong Ho Lee

Inventor： Eun-Chul Ahn ,  Min-Ho O ,  Jong Ho Lee

IPC: H01L23/02

CPC classification number: H01L23/13 ,  H01L23/5389 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/185 ,  H05K2201/09509 ,  H05K2201/10515 ,  H05K2201/10719 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/01049

Abstract: A device includes a base substrate, a package including an encapsulated die, the package at least partially embedded in the base substrate, and a wiring portion on the package and extending across at least a portion of the base substrate adjacent to the package.

Abstract translation: 一种器件包括基底，包括封装的芯片的封装，至少部分地嵌入基底衬底中的封装以及封装上的布线部分，并延伸穿过与封装相邻的基底衬底的至少一部分。

公开(公告)号：US07872297B2

公开(公告)日：2011-01-18

申请号：US11736114

申请日：2007-04-17

Applicant: Jong-Ho Lee

Inventor： Jong-Ho Lee

IPC: H01L29/788

CPC classification number: H01L29/66833 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/42336 ,  H01L29/42348 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/785 ,  H01L29/7881 ,  H01L29/7887 ,  H01L29/792 ,  H01L29/7923

Abstract: The present invention relates to a flash memory device and its fabrication method. The device comprises a structure for improving a scaling-down characteristic/performance and increasing memory capacity of the MOS-based flash memory device. A new device structure according to the present invention is based on a recessed channel capable of implementing highly-integrated/high-performance and 2-bit/cell. The proposed device suppresses the short channel effect, reduces the cell area, and enables 2-bit/cell by forming the charge storage node as a spacer inside the recessed channel. Moreover, if selectively removing the dielectric films around the recessed silicon surface, the sides as well as the surface of the recessed channel is exposed. A spacer can be used as a storage node, thereby improving the channel controllability of the control electrode and the on-off characteristic of a device. The proposed structure also resolves the threshold voltage problem and improves the write/erase speeds.

Abstract translation: 本发明涉及一种闪速存储器件及其制造方法。 该装置包括用于提高缩小特性/性能并增加基于MOS的闪存装置的存储容量的结构。 根据本发明的新器件结构基于能够实现高度集成/高性能和2位/单元的凹陷通道。 所提出的装置抑制短信道效应，减小信元面积，并且通过在电荷存储节点中形成作为凹陷通道内的隔离物来实现2位/单元。 此外，如果选择性地去除凹陷硅表面周围的电介质膜，则侧面以及凹槽的表面被暴露。 可以使用间隔件作为存储节点，从而提高控制电极的通道可控性和设备的开 - 关特性。 所提出的结构还解决了阈值电压问题，提高了写入/擦除速度。

公开(公告)号：US20100285394A1

公开(公告)日：2010-11-11

申请号：US12438619

申请日：2006-12-08

Applicant: Jong-Ho Lee ,  Hae-Weon Lee ,  Joo-Sun Kim ,  Hue-Sup Song ,  Ji-Won Son ,  Hae-Ryoung Kim ,  Sung-Moon Kim ,  Hyoung-Chul Kim ,  Hwa-Young Jung

Inventor： Jong-Ho Lee ,  Hae-Weon Lee ,  Joo-Sun Kim ,  Hue-Sup Song ,  Ji-Won Son ,  Hae-Ryoung Kim ,  Sung-Moon Kim ,  Hyoung-Chul Kim ,  Hwa-Young Jung

IPC: H01M2/08

CPC classification number: H01M8/0282

Abstract: The present invention provides a hybrid composite sealant, as a sealing material for a planar type solid oxide fuel cell stack, having a matrix of a glass composition, wherein a surface layer reinforced with platelet reinforcement particles is laminated on either one or both surfaces of an inner layer reinforced with fibrous reinforcement particles. Accordingly, by applying the composite sealant of the present invention to the solid oxide fuel cell stack, excellent gas-tightness of the stack can be obtained even under low coupling pressure, thermal cycling durability can be enhanced due to low coupling strength with a contact surface of an object to be sealed, stack disassembly and maintenance can be facilitated when parts within the stack are disabled, and stack stability as well as stack performance can be maintained under a pressurized operation condition where pressure differentials between the inside and outside of the stack reach to 5 atmospheric pressures (0.5 MPa).

Abstract translation: 本发明提供一种作为平面型固体氧化物燃料电池堆的密封材料的混合复合密封剂，其具有玻璃组合物的基体，其中用片状增强颗粒增强的表面层层叠在一个或两个表面上 内层用纤维增强颗粒增强。 因此，通过将本发明的复合密封剂应用于固体氧化物型燃料电池组，即使在低耦合压力下也能获得优异的气密性，因为与接触面的低耦合强度可以提高热循环耐久性 当堆中的部件被禁用时，可以方便地进行堆封拆卸和维护，堆叠的稳定性以及堆叠性能可以在叠层内外的压差达到的加压运行状态下保持 至5个大气压（0.5MPa）。