公开(公告)号：US20060160366A1

公开(公告)日：2006-07-20

申请号：US11078435

申请日：2005-03-14

Applicant: Hung Lu ,  Hong Long Chang ,  Yung Kai Lee ,  Chih Hao Chang

Inventor： Hung Lu ,  Hong Long Chang ,  Yung Kai Lee ,  Chih Hao Chang

IPC: H01L21/461

CPC classification number: H01L21/32139 ,  H01L21/3086

Abstract: The present invention discloses a method for preparing a structure with high aspect ratio, which can be a trench or a conductor. A first mask is formed on a substrate, and a first etching process is performed to remove the substrate uncovered by the first mask to form at least one concave. A second mask is formed on the surface of the prepared structure, a second etching process is then performed to remove the second mask on the concave, and a third etching process is performed subsequently to extend the depth of the concave into the substrate. To prepare a conductor with high aspect ratio in the substrate, the first mask and the second mask are preferably made of dielectric material or metal. In addition, to prepare a trench with high aspect ratio in a silicon substrate, the first mask and the second mask are preferably made of dielectric material.

Abstract translation: 本发明公开了一种制备具有高纵横比的结构的方法，其可以是沟槽或导体。 第一掩模形成在衬底上，并且执行第一蚀刻工艺以去除未被第一掩模覆盖的衬底以形成至少一个凹部。 在制备的结构的表面上形成第二掩模，然后执行第二蚀刻工艺以去除凹部上的第二掩模，并且随后执行第三蚀刻工艺以将凹入深度延伸到衬底中。 为了在衬底中制备具有高纵横比的导体，第一掩模和第二掩模优选由介电材料或金属制成。 此外，为了在硅衬底中制备具有高纵横比的沟槽，第一掩模和第二掩模优选由电介质材料制成。

公开(公告)号：US20060110886A1

公开(公告)日：2006-05-25

申请号：US11324454

申请日：2006-01-03

Applicant: Chen-Liang Chu

Inventor： Chen-Liang Chu

IPC: H01L21/336

CPC classification number: H01L21/28211 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28176 ,  H01L29/42368 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A MOSFET structure and a method of forming it are described. The thickness of a portion of the gate dielectric layer of the MOSFET structure adjacent to the drain region is increased to form a bird's beak structure. The gate-to-drain overlap capacitance is reduced by the bird's beak structure.

Abstract translation: 描述MOSFET结构及其形成方法。 与漏极区相邻的MOSFET结构的栅极电介质层的一部分的厚度增加以形成鸟的喙结构。 通过鸟的喙结构减小了栅极到漏极的重叠电容。

公开(公告)号：US07047469B2

公开(公告)日：2006-05-16

申请号：US09808989

申请日：2001-03-16

Applicant: Kang-Mien Chiu

Inventor： Kang-Mien Chiu

IPC: G01R31/28

CPC classification number: H01L22/20

Abstract: A method of searching for and sorting failure signatures of wafers is provided. First, a failure signature database is built up for recording a plurality of failure signature data, wherein each failure signature data includes a failure signature, a location field for the faulty dies, a failure mode, a position dependence information and a dependent signature. Next, a selected wafer is tested and a test result is generated. Last, a comparison result is generated by an automatic comparing device, wherein the comparison result includes a hit or a miss. When the comparison result is a hit, the comparison result further includes a hit ratio. And as the hit ratio exceeds a predetermined value, the step of comparing the dependent signature of the failure signature database is skipped.

Abstract translation: 提供了一种搜索和排序晶片故障签名的方法。 首先，构建用于记录多个故障签名数据的故障签名数据库，其中每个故障签名数据包括故障签名，故障模块的位置字段，故障模式，位置依赖信息和从属签名。 接下来，测试所选择的晶片并产生测试结果。 最后，通过自动比较装置产生比较结果，其中比较结果包括命中或未命中。 当比较结果是命中时，比较结果进一步包括命中率。 并且当命中率超过预定值时，跳过比较故障签名数据库的依赖签名的步骤。

公开(公告)号：US20060091478A1

公开(公告)日：2006-05-04

申请号：US10980165

申请日：2004-11-04

Applicant: Cheng Lee ,  Chih Chuang ,  Tai Chen

Inventor： Cheng Lee ,  Chih Chuang ,  Tai Chen

IPC: H01L29/06

CPC classification number: H01L21/28114 ,  H01L21/28061 ,  H01L21/76897

Abstract: A semiconductor gate structure is described, which comprises a substrate, a gate oxide positioned on the substrate, a first conductive layer positioned on the gate oxide and a second conductive layer positioned on the first conductive layer. The second conductive layer comprises a bottom portion positioned on the first conductive layer, and an upper portion positioned on the bottom portion. The width of the bottom portion is equal to that of the first conductive layer, and one side of the upper portion is aligned to one side of the bottom potion, wherein the other side of the upper portion possesses at least a lateral concave. A bit-line contact metal is subsequently formed next to the concave.

Abstract translation: 描述了半导体栅极结构，其包括衬底，位于衬底上的栅极氧化物，位于栅极氧化物上的第一导电层和位于第一导电层上的第二导电层。 第二导电层包括位于第一导电层上的底部和位于底部的上部。 底部的宽度等于第一导电层的宽度，并且上部的一侧与底部的一侧对准，其中上部的另一侧至少具有侧凹。 随后在凹部附近形成位线接触金属。

公开(公告)号：US07039822B2

公开(公告)日：2006-05-02

申请号：US10375575

申请日：2003-02-27

Applicant: Jon Allan Faue ,  Harold Brett Meadows

Inventor： Jon Allan Faue ,  Harold Brett Meadows

IPC: G06F13/42 ,  H04L7/00

CPC classification number: G11C11/4085 ,  G06F17/505 ,  G06F2217/62 ,  G11C7/10 ,  G11C7/222 ,  G11C11/4097

Abstract: An integrated circuit memory architecture with selectively offset data and address delays to minimize skew and provide synchronization of signals at the input/output section in which the architecture is divided into memory sections, depending upon their distance from the address/control generation block. The address and clock information is re-driven between these sections, which effectively serves to add a quantized number of gate delays in the address path between the sections while concomitantly minimizing skew. A corresponding number of gate delays is also added to the “read” data path for each section such that the number of delays in the address/clock path plus the number of delays in the “read” data path is substantially constant.

Abstract translation: 具有选择性地偏移数据和地址延迟的集成电路存储器架构，以根据它们与地址/控制生成块的距离，将结构被分成存储器部分的输入/输出部分处的信号最小化提供信号的同步。 地址和时钟信息在这些区段之间重新驱动，这有助于在段之间的地址路径中添加量化数量的门延迟，同时最小化偏差。 对于每个部分，相应数量的门延迟也被添加到“读取”数据路径，使得地址/时钟路径中的延迟数加上“读取”数据路径中的延迟数量基本上是恒定的。

公开(公告)号：US07037792B2

公开(公告)日：2006-05-02

申请号：US10877591

申请日：2004-06-25

Applicant: John Lee ,  Barbara A. Haselden

Inventor： John Lee ,  Barbara A. Haselden

IPC: H01L21/336

CPC classification number: H01L21/28238 ,  H01L21/28123 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/823481

Abstract: Isotropic etching of sacrificial oxide that is adjacent to a trench fill step in an STI wafer can lead to undesired etching away of a sidewall of the trench fill material (e.g., HDP oxide). A sidewall protecting method conformably coats the trench fill step and sacrificial oxide with an etch-resistant carbohydrate. In one embodiment, conforming ARC fluid is spun-on and hardened. A selective, dry plasma etches the hardened ARC over the sacrificial oxide while leaving intact part of the ARC that adheres to the trench fill sidewall. The remnant sidewall material defines a protective shroud which delays the subsequent isotropic etchant (e.g., wet HF solution) from immediately reaching the sidewall of the trench fill material. The delay length of the shroud can be controlled by tuning the etchback recipe. In one embodiment, the percent oxygen in an O2 plus Cl2 plasma and/or bias power during the plasma etch is used as a tuning parameter.

Abstract translation: 与STI晶片中的沟槽填充步骤相邻的牺牲氧化物的各向同性蚀刻可导致沟槽填充材料的侧壁（例如，HDP氧化物）的不希望的蚀刻。 侧壁保护方法使用沟槽填充步骤和牺牲氧化物与耐蚀刻碳水化合物一致地涂覆。 在一个实施例中，将适合的ARC流体旋转并硬化。 选择性，干燥的等离子体在牺牲氧化物上蚀刻硬化的ARC，同时留下附着到沟槽填充侧壁的ARC的完整部分。 残余侧壁材料限定了保护罩，其延伸随后的各向同性蚀刻剂（例如，湿HF溶液）从即将到达沟槽填充材料的侧壁。 可以通过调整回蚀配方来控制护罩的延迟长度。 在一个实施例中，在等离子体蚀刻期间，O 2 O 2 + Cl 2等离子体中的氧含量和/或偏置功率用作调谐参数。

公开(公告)号：US07030441B2

公开(公告)日：2006-04-18

申请号：US10986877

申请日：2004-11-15

Applicant: Yung-Hsien Wu ,  Cheng-Che Lee

Inventor： Yung-Hsien Wu ,  Cheng-Che Lee

IPC: H01L29/76 ,  H01L29/94

CPC classification number: H01L21/02326 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02337 ,  H01L21/3144 ,  H01L21/3185 ,  H01L27/10835 ,  H01L27/1087 ,  H01L29/66181

Abstract: A capacitor dielectric structure of a deep trench capacitor for a DRAM cell is disclosed. A semiconductor silicon substrate is provided with a deep trench. Silicon nitride deposition is used to form a silicon nitride layer on the sidewall and bottom of the deep trench. An oxynitride process with wet oxidation and N2O reactive gas is used to form an oxynitride layer on the silicon nitride layer. A post oxynitride growth annealing is performed on the oxynitride layer.

Abstract translation: 公开了用于DRAM单元的深沟槽电容器的电容器电介质结构。 半导体硅衬底设置有深沟槽。 氮化硅沉积用于在深沟槽的侧壁和底部上形成氮化硅层。 使用具有湿氧化和N2O反应气体的氧氮化物工艺在氮化硅层上形成氧氮化物层。 在氧氮化物层上进行氧氮化后生长退火。

公开(公告)号：US20060079080A1

公开(公告)日：2006-04-13

申请号：US10964317

申请日：2004-10-12

Applicant: Kuei-Chang Tsai ,  Chunyuan Chao ,  Chia-Shun Hsiao

Inventor： Kuei-Chang Tsai ,  Chunyuan Chao ,  Chia-Shun Hsiao

IPC: H01L21/4763

CPC classification number: H01L21/76805 ,  H01L21/76802 ,  H01L21/76831

Abstract: A contact via to a surface of a semiconductor material is provided, the contact via having a sidewall which is produced by anisotropically etching a dielectric layer which is placed on via openings. A protective layer is provided on the surface of the semiconductor material. To protect the substrate, an initial etch through an interlayer dielectric is performed to create an initial via which extends toward, but not into the substrate. At least a portion of the protective layer is retained on the substrate. In another step, the final contact via is created. During this step the protective layer is penetrated to open a via to the surface of the semiconductor material.

Abstract translation: 提供了通过半导体材料的表面的接触通孔，该接触通孔具有通过各向异性蚀刻放置在通孔上的电介质层产生的侧壁。 在半导体材料的表面上设置保护层。 为了保护衬底，进行通过层间电介质的初始蚀刻，以产生向衬底延伸但不延伸到衬底中的初始通孔。 保护层的至少一部分保留在基板上。 在另一步中，创建最终的联系人通道。 在该步骤期间，保护层被穿透以将通孔打开到半导体材料的表面。

公开(公告)号：US20060076601A1

公开(公告)日：2006-04-13

申请号：US10980225

申请日：2004-11-04

Applicant: Rui-Yuan Hon ,  Tony Chien

Inventor： Rui-Yuan Hon ,  Tony Chien

IPC: H01L29/94 ,  H01L21/8242

CPC classification number: H01L27/0207 ,  H01L27/10867 ,  H01L27/10888 ,  Y10S257/905

Abstract: A dynamic random access memory structure is provided, each active area of a memory unit cell is distributed individually in a substrate, and deep trench patterns are designed to have a checkerboard-like arrangement in the substrate. Also, there is a constant space between each deep trench pattern in a row. Further, long bit line contact plugs are located to electrically connect active areas of two diagonally neighbor memory unit cells, and a contact hole is formed on each long bit line contact plug to enable bit lines contact the long bit line contact plugs so two diagonally neighbor memory unit cells are controlled by the same bit line.

Abstract translation: 提供了动态随机存取存储器结构，存储单元单元的每个有源区域分别分布在衬底中，并且深沟槽图案被设计为在衬底中具有棋盘状布置。 此外，在一排中的每个深沟槽图案之间存在恒定的空间。 此外，长位线接触插头被定位成电连接两个对角相邻存储单元电池的有源区，并且在每个长位线接触插塞上形成接触孔，以使位线接触长位线接触插塞，使得两个对角线邻近 存储器单元由相同的位线控制。

公开(公告)号：US07026172B2

公开(公告)日：2006-04-11

申请号：US10033114

申请日：2001-10-22

Applicant: Tai-Peng Lee ,  Chuck Jang

Inventor： Tai-Peng Lee ,  Chuck Jang

IPC: H01L21/3065

CPC classification number: H01L21/02164 ,  C23C16/045 ,  C23C16/50 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31612 ,  H01L21/76229

Abstract: A high density plasma chemical vapor deposition (HDP-CVD) process is used to deposit silicon dioxide in trenches of various widths. The thickness of the silicon dioxide filling both narrow and wide trenches is made more uniform by reducing an HDP-CVD etch to deposition ratio. The lowered etch to deposition ratio is achieved by lowering a ratio of oxygen to silane gas, by lowering the power of a high frequency bias signal, and by lowering the total gas flow rate.

Abstract translation: 使用高密度等离子体化学气相沉积（HDP-CVD）工艺将二氧化硅沉积在各种宽度的沟槽中。 通过将HDP-CVD蚀刻减少到沉积比，使填充窄和宽沟槽的二氧化硅的厚度变得更均匀。 通过降低氧气与硅烷气体的比例，通过降低高频偏置信号的功率和降低总气体流量来实现降低的蚀刻到沉积比。