公开(公告)号：US11316024B2

公开(公告)日：2022-04-26

申请号：US17165934

申请日：2021-02-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Xian Liu ,  Guo Xiang Song ,  Leo Xing ,  Nhan Do

IPC: G11C11/34 ,  H01L29/423 ,  H01L29/788 ,  H01L29/66 ,  G11C16/04

Abstract: A memory device, and method of making the same, that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and having a second conductivity type different than the first conductivity type, with a first channel region in the substrate extending between the first and second regions, a first floating gate disposed over and insulated from a first portion of the first channel region adjacent to the second region, a first coupling gate disposed over and insulated from the first floating gate, a first word line gate disposed over and insulated from a second portion of the first channel region adjacent the first region, and a first erase gate disposed over and insulated from the first word line gate.

公开(公告)号：US20220101920A1

公开(公告)日：2022-03-31

申请号：US17152696

申请日：2021-01-19

Applicant: Silicon Storage Technology, Inc.

Inventor： CHUNMING WANG ,  XIAN LIU ,  GUO XIANG SONG ,  LEO XING ,  NHAN DO

IPC: G11C16/04 ,  G11C16/16 ,  H01L29/423 ,  H01L27/11521 ,  H01L27/11556

Abstract: A memory device includes a semiconductor substrate, first and second regions in the substrate having a conductivity type different than that of the substrate, with a channel region in the substrate extending between the first and second regions. The channel region is continuous between the first and second regions. A first floating gate is disposed over and insulated from a first portion of the channel region. A second floating gate is disposed over and insulated from a second portion of the channel region. A first coupling gate is disposed over and insulated from the first floating gate. A second coupling gate is disposed over and insulated from the second floating gate. A word line gate is disposed over and insulated from a third portion of the channel region between the first and second channel region portions. An erase gate is disposed over and insulated from the word line gate.

公开(公告)号：US20220093623A1

公开(公告)日：2022-03-24

申请号：US17151944

申请日：2021-01-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Guo Xiang Song ,  Leo Xing ,  Jack Sun ,  Xian Liu ,  Nhan Do

IPC: H01L27/11531 ,  H01L27/11521 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  H01L21/28 ,  H01L21/265 ,  H01L21/762 ,  H01L29/66

Abstract: A method of forming memory cells, HV devices and logic devices on a substrate, including recessing the upper surface of the memory cell and HV device areas of the substrate, forming a polysilicon layer in the memory cell and HV device areas, forming first trenches through the first polysilicon layer and into the silicon substrate in the memory cell and HV device areas, filling the first trenches with insulation material, forming second trenches into the substrate in the logic device area to form upwardly extending fins, removing portions of the polysilicon layer in the memory cell area to form floating gates, forming erase and word line gates in the memory cell area, HV gates in the HV device area, and dummy gates in the logic device area from a second polysilicon layer, and replacing the dummy gates with metal gates that wrap around the fins.

公开(公告)号：US11270763B2

公开(公告)日：2022-03-08

申请号：US16382045

申请日：2019-04-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do ,  Mark Reiten

IPC: G11C11/54 ,  H01L27/11521 ,  H01L29/423 ,  G11C16/04 ,  G06N3/04 ,  G11C16/10 ,  G11C16/14 ,  H01L29/788

Abstract: A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell rows, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell columns, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or second lines, and provide a first plurality of outputs as electrical currents on the third or fourth lines.

公开(公告)号：US11257553B2

公开(公告)日：2022-02-22

申请号：US17239397

申请日：2021-04-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu

IPC: G11C16/00 ,  G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/16 ,  G11C16/28

Abstract: The present invention relates to a flash memory cell with only four terminals and a high voltage row decoder for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.

公开(公告)号：US20220004860A1

公开(公告)日：2022-01-06

申请号：US17140924

申请日：2021-01-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly ,  Nhan Do ,  Mark Reiten

IPC: G06N3/063 ,  G11C11/408 ,  G11C11/4074 ,  G11C11/406

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. Certain embodiments comprise an adaptive bias decoder for providing additional bias to array input lines to compensate for instances where ground floats above 0V. This is useful, for example, to minimize the voltage drop for a read, program, or erase operation while maintaining accuracy in the operation.

公开(公告)号：US20210407602A1

公开(公告)日：2021-12-30

申请号：US16915289

申请日：2020-06-29

Applicant: Silicon Storage Technology, Inc.

Inventor： Viktor Markov ,  Alexander Kotov

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

Abstract: A method and device for programming a non-volatile memory cell, where the non-volatile memory cell includes a first gate. The non-volatile memory cell is programmed to an initial program state that corresponds to meeting or exceeding a target threshold voltage for the first gate of the non-volatile memory cell. The target threshold voltage corresponds to a target read current. The non-volatile memory cell is read in a first read operation using a read voltage applied to the first gate of the non-volatile memory cell that is less than the target threshold voltage to generate a first read current. The non-volatile memory cell is subjected to additional programming in response to determining that the first read current is greater than the target read current.

公开(公告)号：US20210383869A1

公开(公告)日：2021-12-09

申请号：US17104385

申请日：2020-11-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly

IPC: G11C16/08 ,  G11C11/54 ,  G06N3/063

Abstract: Various embodiments of tandem row decoders are disclosed. Each embodiment of a tandem row decoder comprises a word line decoder and a control gate decoder. The tandem row decoder exhibits reduced leakage current on the word line and the control gate line when the tandem row decoder is not enabled.

公开(公告)号：US20210366522A1

公开(公告)日：2021-11-25

申请号：US17095331

申请日：2020-11-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Massimiliano Frulio

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  H03K19/21

Abstract: A self-timed sensing architecture for reading a selected cell in an array of non-volatile cells is disclosed. The sensing circuitry generates a signal when a stable sensing value has been obtained from the selected cell, where the stable sensing value indicates the value stored in the selected cell. The signal indicates the end of the sensing operation, causing the stable sensing value to be output as the result of the read operation.

公开(公告)号：US20210350217A1

公开(公告)日：2021-11-11

申请号：US17090481

申请日：2020-11-05

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Vipin Tiwari ,  Han Tran ,  Hien Pham

IPC: G06N3/063

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. Certain embodiments contain improved mechanisms for pulling source lines down to ground expeditiously. This is useful, for example, to minimize the voltage drop for a read, program, or erase operation.