公开(公告)号：US06946821B2

公开(公告)日：2005-09-20

申请号：US10250410

申请日：2001-12-28

Applicant: Cécile Hamon ,  Christophe Bernard ,  Alexandre Pons

Inventor： Cécile Hamon ,  Christophe Bernard ,  Alexandre Pons

IPC: G05F1/565 ,  G05F3/26

CPC classification number: G05F1/565 ,  G05F3/262

Abstract: A voltage regulator having an output terminal adapted to being connected to a load, including an operational amplifier having its non-inverting input connected to a reference voltage, and its inverting input connected to the output terminal, an inverting amplifier having its input connected to the output of the operational amplifier, a capacitive impedance connected between the input and the output of the inverting amplifier, a power switch controlled by the output of the inverter amplifier, arranged to connect the output terminal to a first supply voltage, said capacitive impedance including a short-circuitable portion associated with active short-circuit means when the current flowing through the load is greater than a predetermined current.

Abstract translation: 一种电压调节器，其具有适于连接到负载的输出端子，包括具有连接到参考电压的其非反相输入的运算放大器，以及连接到输出端子的反相输入端，反相放大器的输入端连接到 运算放大器的输出，连接在反相放大器的输入和输出端之间的电容性阻抗，由反相放大器的输出控制的功率开关，被布置成将输出端连接到第一电源电压，所述电容性阻抗包括 当流过负载的电流大于预定电流时，与主动短路相关联的短路部分意味着。

公开(公告)号：US20050195637A1

公开(公告)日：2005-09-08

申请号：US11063651

申请日：2005-02-22

Applicant: Jose Martino ,  Enrico Castaldo ,  Nicolas Demange ,  Daniele Zompi

Inventor： Jose Martino ,  Enrico Castaldo ,  Nicolas Demange ,  Daniele Zompi

IPC: G11C5/14 ,  G11C11/24 ,  G11C16/04 ,  G11C16/24 ,  G11C16/30 ,  G11C29/00

CPC classification number: G11C5/147 ,  G11C16/0441 ,  G11C16/24 ,  G11C16/30 ,  G11C29/846

Abstract: A biasing structure for a memory cell storage element, for setting an operating voltage at an accession electrode of the memory cell storage element. The biasing structure includes a biasing transistor coupled to the accession electrode and adapted to set the operating voltage based on a biasing voltage received at a control electrode of the biasing transistor, and a biasing voltage generator for generating the biasing voltage. The biasing voltage generator includes a feedback voltage regulation structure adapted track changes in a threshold voltage of the biasing transistor, so as to keep the operating voltage at the accession electrode of the memory cell storage element substantially stable against operating condition changes.

Abstract translation: 一种用于存储单元存储元件的偏置结构，用于设置存储单元存储元件的寄存电极处的工作电压。 偏置结构包括耦合到寄存电极的偏置晶体管，并且适于基于在偏置晶体管的控制电极处接收的偏置电压来设置工作电压;以及偏置电压发生器，用于产生偏置电压。 偏置电压发生器包括适应偏置晶体管的阈值电压的轨道变化的反馈电压调节结构，以便保持存储单元存储元件的入门电极处的工作电压对于操作条件变化基本上是稳定的。

公开(公告)号：US06940319B2

公开(公告)日：2005-09-06

申请号：US10616451

申请日：2003-07-09

Applicant: Laurent Dulau ,  Serge Pontarollo

Inventor： Laurent Dulau ,  Serge Pontarollo

IPC: H03K4/00 ,  H03K17/16 ,  H03K17/687 ,  H03K3/00

CPC classification number: H03K4/00 ,  H03K17/163 ,  H03K17/168 ,  H03K17/6877

Abstract: A device for controlling a voltage-controlled switch, including two circuits respectively for setting to the high level and for setting to the low level a control terminal of the voltage-controlled switch, one at least of the circuits including a power transistor capable of connecting the control terminal to a high, respectively low voltage, a bipolar control transistor having its emitter, respectively its collector, connected to the control terminal of the power transistor, the base of the control transistor being likely to receive a control current and a first diode connected between a first predetermined voltage smaller than the high voltage, and the base of the control transistor.

Abstract translation: 一种用于控制压控开关的装置，包括分别设置为高电平的两个电路和用于将电压控制开关的控制端设置为低电平的装置，至少一个电路包括能够连接的功率晶体管 控制端子分别连接到功率晶体管的控制端子，分别具有其发射极和发射极的双极性控制晶体管，高电平，低电压，控制晶体管的基极可能接收控制电流，第一二极管 连接在小于高电压的第一预定电压和控制晶体管的基极之间。

公开(公告)号：US20050191818A1

公开(公告)日：2005-09-01

申请号：US11123318

申请日：2005-05-06

Applicant: Michel Marty ,  Philippe Coronel ,  Francois Leverd

Inventor： Michel Marty ,  Philippe Coronel ,  Francois Leverd

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/08 ,  H01L29/417 ,  H01L29/732

CPC classification number: H01L29/66272 ,  H01L29/0821 ,  H01L29/41708

Abstract: An integrated circuit including a buried layer of determined conductivity type in a plane substantially parallel to the plane of a main circuit surface, in which the median portion of this buried layer is filled with a metal-type material.

Abstract translation: 一种集成电路，其包括在基本上平行于主电路表面的平面的平面中确定的导电类型的掩埋层，其中该掩埋层的中间部分填充有金属型材料。

公开(公告)号：US06927352B2

公开(公告)日：2005-08-09

申请号：US10841180

申请日：2004-05-07

Applicant: Guillaume Bouche ,  Daniel Saias

Inventor： Guillaume Bouche ,  Daniel Saias

IPC: H01H59/00 ,  H01H61/02 ,  H01H13/70 ,  H01N9/00

CPC classification number: H01H59/0009 ,  H01H61/02 ,  H01H2001/0063 ,  H01H2001/0068 ,  H01H2061/006

Abstract: A multiposition microswitch that includes a cavity, a mobile portion made of a deformable material extending above the cavity, at least three conductive tracks extending on the cavity bottom, and a contact pad on the lower surface of the mobile part. The mobile part is capable of deforming, under the action of a stressing mechanism, from an idle position where the contact pad is distant from the conductive tracks to an on position from among several distinct on positions. The contact pad electrically connects, in each distinct on position, at least two of the at least three conductive tracks, at least one of the conductive tracks connected to the contact pad in each distinct on position being different from the conductive tracks connected to the contact pad in the other distinct on positions.

Abstract translation: 一种多位微动开关，其包括空腔，由空腔上方延伸的可变形材料制成的移动部分，在空腔底部延伸的至少三个导电轨道，以及在所述移动部件的下表面上的接触垫。 移动部件能够在应力机构的作用下从接触垫远离导电轨道的空闲位置变形到几个不同的位置之间的打开位置。 接触焊盘在每个不同的位置上电连接至少三个导电轨道中的至少两个，至少一个导电轨道在每个不同的位置上连接到接触焊盘，其不同于连接到触点的导电轨迹 垫在另一个不同的位置。

公开(公告)号：US20050172185A1

公开(公告)日：2005-08-04

申请号：US11046381

申请日：2005-01-28

Applicant: Frederic Bancel ,  David Hely

Inventor： Frederic Bancel ,  David Hely

IPC: G01R31/317 ,  G01R31/3185 ,  G06F12/14 ,  G06F21/75 ,  G06F7/38 ,  G01R31/28 ,  H03K19/173 ,  H03K19/177

CPC classification number: G06F21/75 ,  G01R31/31719 ,  G01R31/318533

Abstract: An electronic circuit, having a test mode in application of the “internal scan path” technique, includes a plurality of configurable cells and a control circuit. The electronic circuit is adapted to working in a standard mode of operation or in a test mode during which the control circuit is active and configures the configurable cells either in a functional state or in a chained state. The electronic circuit furthermore includes a validation circuit that performs the following operations successively when it receives an instruction for changing the mode of operation (TEST, FIN) of the electronic circuit: produce initialization signals (INIT1, INIT2, . . . , INITN) to command the initialization of all the configurable cells, and then produce a mode-changing signal (VAL).

Abstract translation: 具有应用“内部扫描路径”技术的测试模式的电子电路包括多个可配置单元和控制电路。 电子电路适于在标准操作模式或测试模式下工作，在该模式期间，控制电路处于活动状态，并且将可配置单元配置为处于功能状态或处于链状态。 电子电路还包括验证电路，当接收到用于改变电子电路的操作模式（TEST，FIN）的指令时，连续地执行以下操作：产生初始化信号（INIT 1，INIT 2，...，INITN ）来命令所有可配置单元的初始化，然后产生模式改变信号（VAL）。

公开(公告)号：US06924546B2

公开(公告)日：2005-08-02

申请号：US10489153

申请日：2002-09-10

Applicant: Emmanuel Collard ,  Patrick Poveda

Inventor： Emmanuel Collard ,  Patrick Poveda

IPC: H01L29/861 ,  H01L29/868 ,  H01L31/105

CPC classification number: H01L29/868 ,  H01L29/8613

Abstract: The invention concerns a low-capacity vertical diode designed to be mounted by a front surface made in a semiconductor substrate (1), comprising a first zone projecting relative to the surface of the substrate including at least a semiconductor layer (3) doped with a type of conductivity opposite to that of the substrate, the upper surface of the semiconductor layer bearing a first solder bump (23). The diode comprises a second zone including on the substrate a thick strip conductor (16) bearing at least second solder bumps (24), said first and second solder bumps defining a plane parallel to the substrate plane.

Abstract translation: 本发明涉及一种设计成由半导体衬底（1）制成的前表面安装的低容量垂直二极管，包括相对于衬底的表面突出的第一区域，该第一区域包括至少掺杂有半导体衬底的半导体层（3） 类型的导电性与衬底的导电性相反，半导体层的上表面具有第一焊料凸点（23）。 所述二极管包括第二区域，所述第二区域在所述衬底上具有承载至少第二焊料凸块（24）的厚条状导体（16），所述第一和第二焊料凸块限定平行于所述衬底平面的平面。

公开(公告)号：US06922614B2

公开(公告)日：2005-07-26

申请号：US10697792

申请日：2003-10-30

Applicant: Maurice Le Van Suu ,  Michel Romet

Inventor： Maurice Le Van Suu ,  Michel Romet

IPC: H02J13/00 ,  G06F19/00

CPC classification number: H02J13/0075 ,  Y02E60/7853 ,  Y04S40/126

Abstract: This invention relates to an energy management system in an energy distribution network (DSTR) comprising an energy source (SE1) and a number of energy consumers (K1, K2, K3) distributed in different consumption locations, this system comprising the installation of distributed energy operation means (RXE) and distributed information transmission means (RTI) in each consumption location, and installation of centralised distributed energy management means (CGED) and centralised information transmission means (CTI) in the network (DSTR), transmitting control signals (SC) to the distributed energy operation means (RXE) passing through the distributed information transmission means (RTI).

Abstract translation: 本发明涉及一种能量分配网络（DSTR）中的能量管理系统，该能量管理系统包括分布在不同消耗位置的能量源（SE1）和多个能量消耗器（K 1，K 2，K 3），该系统包括 在每个消费位置安装分布式能量操作装置（RXE）和分布式信息传输装置（RTI），以及在网络（DSTR）中安装集中式分布式能量管理装置（CGED）和集中式信息传输装置（CTI），传输控制 信号（SC）发送到通过分布式信息传输装置（RTI）的分布式能量操作装置（RXE）。

公开(公告)号：US20050160245A1

公开(公告)日：2005-07-21

申请号：US11016325

申请日：2004-12-17

Applicant: Alain Artieri

Inventor： Alain Artieri

IPC: G06F5/10 ,  G11C7/10 ,  G11C11/419 ,  G06F12/00

CPC classification number: G11C11/419 ,  G06F5/10

Abstract: A FIFO memory with a frequency f and a size of M n-bit words, to successively store n-bit words received serially at an input and give said words serially at an output in the order in which they are stored, comprises a basic memory with a frequency f/2, capable of simultaneously storing two n-bit words successively received at the input of the FIFO memory. The memory also comprises a storage circuit to store either one n-bit word received at the input of the FIFO memory or simultaneously two n-bit words produced by the basic memory and to produce, at the output OUT of the FIFO memory, one of the words that said storage circuit stores.

Abstract translation: 具有频率f和M个n位字的大小的FIFO存储器，以连续地存储在输入处串行接收的n位字，并以其存储顺序在输出处串行地给出所述字，包括基本存储器 具有频率f / 2，能够同时存储在FIFO存储器的输入端连续接收的两个n位字。 存储器还包括存储电路，用于存储在FIFO存储器的输入处接收到的一个n位字，或者同时存储由基本存储器产生的两个n位字，并且在FIFO存储器的输出OUT处产生 所述存储电路存储的字。

公开(公告)号：US06919614B2

公开(公告)日：2005-07-19

申请号：US10774896

申请日：2004-02-09

Applicant: Fabrice Blisson ,  Gilles Debeurme

Inventor： Fabrice Blisson ,  Gilles Debeurme

IPC: H01L23/528 ,  H01L27/02 ,  H01L29/00

CPC classification number: H01L27/0203 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit with a D.C./D.C. voltage regulator and its manufacturing process, including at least one power stage provided with at least two transistors and with at least one capacitor connecting a control electrode of the transistor to a reference voltage, a same control stage of the regulator providing a control signal of said transistors, the power stage being formed under a rail that provides supply signals of the integrated circuit, the rail providing at least two limiting supply voltages coming from the outside of the integrated circuit and at least one voltage regulated by the voltage regulator.

Abstract translation: 具有D.C./D.C的集成电路。 电压调节器及其制造过程，包括至少一个设置有至少两个晶体管的功率级以及将晶体管的控制电极连接到参考电压的至少一个电容器，调节器的相同控制级提供所述 晶体管，所述功率级形成在提供所述集成电路的电源信号的轨道下方，所述轨道提供来自所述集成电路的外部的至少两个限制电源电压和由所述电压调节器调节的至少一个电压。