公开(公告)号：US20120237877A1

公开(公告)日：2012-09-20

申请号：US13049123

申请日：2011-03-16

Applicant: Hung-Chun Wang ,  Pei-Shiang Chen ,  Tzu-Chin Lin ,  Faruk Krecinic ,  Jeng-Horng Chen ,  Wen-Chun Huang ,  Ru-Gun Liu

Inventor： Hung-Chun Wang ,  Pei-Shiang Chen ,  Tzu-Chin Lin ,  Faruk Krecinic ,  Jeng-Horng Chen ,  Wen-Chun Huang ,  Ru-Gun Liu

IPC: G03F7/20 ,  G06F17/50

CPC classification number: H01J37/3026 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/20 ,  G03F1/36 ,  G03F7/2037 ,  H01J37/3174 ,  H01J2237/063 ,  H01J2237/31762 ,  H01J2237/31764 ,  Y10S430/143

Abstract: The present disclosure provides for many different embodiments of a charged particle beam data storage system and method. In an example, a method includes dividing a design layout into a plurality of units; creating a lookup table that maps each of the plurality of units to its position within the design layout and a data set, wherein the lookup table associates any repeating units in the plurality of units to a same data set; and exposing an energy sensitive layer to a charged particle beam based on the lookup table.

Abstract translation: 本公开提供了带电粒子束数据存储系统和方法的许多不同实施例。 在一个示例中，一种方法包括将设计布局划分成多个单元; 创建将所述多个单元中的每一个映射到其在所述设计布局内的位置和数据集合的查找表，其中所述查找表将所述多个单元中的任何重复单元关联到相同的数据集; 并且基于查找表将能量敏感层暴露于带电粒子束。

公开(公告)号：US20120187563A1

公开(公告)日：2012-07-26

申请号：US13012211

申请日：2011-01-24

Applicant: Ya-Hsueh HSIEH ,  Teng-Chun Tsai ,  Wen-Chin Lin ,  Hsin-Kuo Hsu ,  Ren-Peng Huang ,  Chih-Hsien Chen ,  Chih-Chin Yang ,  Hung-Yuan Lu ,  Jen-Chieh Lin ,  Wei-Che Tsao

Inventor： Ya-Hsueh HSIEH ,  Teng-Chun Tsai ,  Wen-Chin Lin ,  Hsin-Kuo Hsu ,  Ren-Peng Huang ,  Chih-Hsien Chen ,  Chih-Chin Yang ,  Hung-Yuan Lu ,  Jen-Chieh Lin ,  Wei-Che Tsao

IPC: H01L23/532 ,  H01L21/28

CPC classification number: H01L21/7684 ,  H01L21/3212 ,  H01L29/4966 ,  H01L29/517

Abstract: A planarization method of manufacturing a semiconductor component is provided. A dielectric layer is formed above a substrate and defines a trench therein. A barrier layer and a metal layer are formed in sequence in the trench. A first planarization process is applied to the metal layer by using a first reactant so that a portion of the metal layer is removed. An etching rate of the first reactant to the metal layer is greater than that of the first reactant to the barrier layer. A second planarization process is applied to the barrier layer and the metal layer by using a second reactant so that a portion of the barrier layer and the metal layer are removed to expose the dielectric layer. An etching rate of the second reactant to the barrier layer is greater than that of the second reactant to the metal layer.

Abstract translation: 提供了制造半导体部件的平面化方法。 介电层形成在衬底之上并在其中限定沟槽。 在沟槽中依次形成阻挡层和金属层。 通过使用第一反应物将第一平面化工艺施加到金属层，使得金属层的一部分被去除。 第一反应物对金属层的蚀刻速率大于第一反应物对阻挡层的蚀刻速率。 通过使用第二反应物将阻挡层和金属层施加第二平坦化工艺，使得去除阻挡层和金属层的一部分以暴露电介质层。 第二反应物对阻挡层的蚀刻速率大于第二反应物对金属层的蚀刻速率。

公开(公告)号：US20120106868A1

公开(公告)日：2012-05-03

申请号：US13286300

申请日：2011-11-01

Applicant: Shih-Chin Lin

Inventor： Shih-Chin Lin

IPC: G06K9/40

CPC classification number: G06T11/001 ,  G06T7/38

Abstract: An image correction apparatus for correcting an original image captured by a photographing device is provided. The image correction apparatus includes a storage and a texture mapping module. The storage therein stores mapping data sets associated with the photographing device. The invention is able to construct and utilize mapping data associated with a particular optical lens when used as part of the photographic device. The texture mapping module corrects an original captured image using a texture mapping procedure according to the appropriate mapping data to generate a corrected image. The texture mapping procedure may use mapping data in a polygon based approach to generate corrected images more efficiently.

Abstract translation: 提供了一种用于校正由拍摄装置拍摄的原始图像的图像校正装置。 图像校正装置包括存储和纹理映射模块。 其中的存储存储与拍摄装置相关联的映射数据集。 当用作照相设备的一部分时，本发明能够构建和利用与特定光学透镜相关联的映射数据。 纹理映射模块使用根据适当的映射数据的纹理映射过程校正原始捕获的图像，以生成校正图像。 纹理映射过程可以使用基于多边形的方法中的映射数据来更有效地生成校正图像。

公开(公告)号：US08103494B2

公开(公告)日：2012-01-24

申请号：US11292628

申请日：2005-12-02

Applicant: Derek Wang ,  Kun-Chi Liu ,  Ta-Chin Lin

Inventor： Derek Wang ,  Kun-Chi Liu ,  Ta-Chin Lin

IPC: G06F17/50 ,  G06F11/30 ,  G06F19/00

CPC classification number: G06Q10/087

Abstract: A management system and method. The system comprises at least one delivery request, a plurality of equipment and a simulator. The delivery request indicates a plurality of devices, each comprising a respective quantity. The equipment tests the devices, each equipment comprising an equipment configuration. The simulator retrieves device configuration requirements of respective devices, maps the devices to the equipment according to the respective device configuration requirements and the equipment configurations to obtain a mapping result, and calculates at least one performance index based on the mapping result and the quantity of respective devices.

Abstract translation: 管理系统和方法。 该系统包括至少一个递送请求，多个设备和模拟器。 递送请求指示多个设备，每个设备包括相应的数量。 设备测试设备，每个设备包括设备配置。 模拟器检索相应设备的设备配置要求，根据各设备配置要求和设备配置将设备映射到设备，以获得映射结果，并根据映射结果和相应的数量计算至少一个性能指标 设备。

公开(公告)号：USD650514S1

公开(公告)日：2011-12-13

申请号：US29387543

申请日：2011-03-15

Applicant: Chih-Chen Lin ,  Wen-Chin Lin ,  Shuh-Hwar Yahn

Designer： Chih-Chen Lin ,  Wen-Chin Lin ,  Shuh-Hwar Yahn

公开(公告)号：US08064108B2

公开(公告)日：2011-11-22

申请号：US11506441

申请日：2006-08-18

Applicant: Chin-Lin Chang ,  Chen-Ho Lee ,  Chen-Hsiang Shih

Inventor： Chin-Lin Chang ,  Chen-Ho Lee ,  Chen-Hsiang Shih

IPC: H04N1/04

CPC classification number: H04N1/00013 ,  H04N1/00002 ,  H04N1/00031 ,  H04N1/00045 ,  H04N1/0005 ,  H04N1/00063 ,  H04N1/00068 ,  H04N1/00087 ,  H04N1/047 ,  H04N1/1013 ,  H04N1/1017 ,  H04N1/193 ,  H04N2201/0081 ,  H04N2201/04708 ,  H04N2201/0472 ,  H04N2201/04727 ,  H04N2201/04749

Abstract: A full-zone optical image addressing apparatus, including an addressing device, an image extraction converter, a comparator, an AND gate and a counter. The addressing device is located at the enclosure of the scanner and includes a plurality of geometric patterns. Each of the geometric patterns includes a plurality of rows of pixels. While receiving an exposure signal, the image extraction converter extracts one row of pixels from the addressing device, such that a series of analog signals is obtained and output to the comparator. The comparator then compares the series of analog signals to an analog critical voltage to output a series of analog comparison signals to the AND gate. The AND gate synchronously processes the series of analog comparison signals and a pixel rate clock to output the pixel data corresponding to the extracted row of pixels to the counter. After receiving the synchronously processed pixel value from the AND gate, the counter calculates and outputs the extracted row of pixels, including the amount of pixels and the geometric patterns in the row of pixels.

Abstract translation: 全区域光学图像寻址装置，包括寻址装置，图像提取转换器，比较器，与门和计数器。 寻址设备位于扫描仪的外壳处并且包括多个几何图案。 每个几何图案包括多行像素。 在接收到曝光信号的同时，图像提取转换器从寻址装置中提取一行像素，从而获得一系列模拟信号并将其输出到比较器。 比较器然后将一系列模拟信号与模拟临界电压进行比较，以将一系列模拟比较信号输出到与门。 与门同时处理一系列模拟比较信号和像素速率时钟，以将与提取的像素行对应的像素数据输出到计数器。 在从与门接收到同步处理的像素值之后，计数器计算并输出所提取的像素行，包括像素行中的像素数量和几何图案。

公开(公告)号：US20110248348A1

公开(公告)日：2011-10-13

申请号：US12756662

申请日：2010-04-08

Applicant: Tian-Choy Gan ,  Hsien-Chin Lin ,  Chia-Pin Lin ,  Shyue-Shyh Lin ,  Li-Shiun Chen ,  Shin Hsien Liao

Inventor： Tian-Choy Gan ,  Hsien-Chin Lin ,  Chia-Pin Lin ,  Shyue-Shyh Lin ,  Li-Shiun Chen ,  Shin Hsien Liao

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/8238 ,  H01L29/66795 ,  H01L29/785

Abstract: Provided is a method of fabricating a semiconductor device that includes forming first and second fins over first and second regions of a substrate, forming first and second gate structures over the first and second fins, the first and second gate structures including first and second poly gates, forming an inter-level dielectric (ILD) over the substrate, performing a chemical mechanical polishing on the ILD to expose the first and second poly gates, forming a mask to protect the first poly gate of the first gate structure, removing the second poly gate thereby forming a first trench, removing the mask, partially removing the first poly gate thereby forming a second trench, forming a work function metal layer partially filling the first and second trenches, forming a fill metal layer filling a remainder of the first and second trenches, and removing the metal layers outside the first and second trenches.

Abstract translation: 提供一种制造半导体器件的方法，该半导体器件包括在衬底的第一和第二区域上形成第一和第二鳍片，在第一和第二鳍片上形成第一和第二栅极结构，第一和第二栅极结构包括第一和第二多晶硅栅极 ，在所述衬底上形成层间电介质（ILD），在所述ILD上进行化学机械抛光以暴露所述第一和第二多晶硅栅极，形成掩模以保护所述第一栅极结构的所述第一多晶硅栅极， 从而形成第一沟槽，去除掩模，部分地移除第一多晶硅栅极，从而形成第二沟槽，形成部分填充第一和第二沟槽的功函数金属层，形成填充第一和第二沟槽的剩余部分的填充金属层 沟槽，并且去除第一和第二沟槽外的金属层。

公开(公告)号：US08034677B2

公开(公告)日：2011-10-11

申请号：US12712594

申请日：2010-02-25

Applicant: Chia-Pin Lin ,  Wen-Sheh Huang ,  Tian-Choy Gan ,  Chia-Lung Hung ,  Hsien-Chin Lin ,  Shyue-Shyh Lin

Inventor： Chia-Pin Lin ,  Wen-Sheh Huang ,  Tian-Choy Gan ,  Chia-Lung Hung ,  Hsien-Chin Lin ,  Shyue-Shyh Lin

IPC: H01L21/336

CPC classification number: H01L29/66795 ,  H01L29/66803

Abstract: Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations such as an LDD or a PKT implant, are carried out in between the two nitride film deposition operations. The first nitride film may be SiN, or SiCNx and the second nitride film is SiCNx with a low wet etch rate in H3PO4 and dilute HF acid. The nitride films may be combined to form low wet etch rate spacers enabling further processing operations to be carried out without damaging underlying structures and without requiring the formation of further dummy spacers. Further processing operations include epitaxial silicon/SiGe processing sequences and source/drain implanting operations carried out with the low etch rate spacers intact.

Abstract translation: 提供了形成在半导体鳍上的高k金属栅极结构。 在栅极结构和半导体鳍片上形成氮化物层，使用两个单独的沉积操作，首先形成非常薄的氮化物膜。 在两个氮化物膜沉积操作之间进行诸如LDD或PKT注入的植入操作。 第一氮化物膜可以是SiN或SiCNx，并且第二氮化物膜是在H3PO4中的低湿蚀刻速率的SiCNx和稀释的HF酸。 可以将氮化物膜组合以形成低湿蚀刻速率间隔物，使得能够进行进一步的处理操作而不损坏下面的结构，而不需要形成另外的虚设间隔物。 进一步的处理操作包括外延硅/ SiGe处理序列和用低蚀刻速率间隔物完整地进行的源极/漏极注入操作。

公开(公告)号：US20110207279A1

公开(公告)日：2011-08-25

申请号：US12712594

申请日：2010-02-25

Applicant: Chia-Pin LIN ,  Wen-Sheh HUANG ,  Tian-Choy GAN ,  Chia-Lung HUNG ,  Hsien-Chin LIN ,  Shyue-Shyh LIN

Inventor： Chia-Pin LIN ,  Wen-Sheh HUANG ,  Tian-Choy GAN ,  Chia-Lung HUNG ,  Hsien-Chin LIN ,  Shyue-Shyh LIN

IPC: H01L21/336

CPC classification number: H01L29/66795 ,  H01L29/66803

Abstract: Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations such as an LDD or a PKT implant, are carried out in between the two nitride film deposition operations. The first nitride film may be SiNx or SiCNx and the second nitride film is SiCNx with a low wet etch rate in H3PO4 and dilute HF acid. The nitride films may be combined to form low wet etch rate spacers enabling further processing operations to be carried out without damaging underlying structures and without requiring the formation of further dummy spacers. Further processing operations include epitaxial silicon/SiGe processing sequences and source/drain implanting operations carried out with the low etch rate spacers intact.

Abstract translation: 提供了形成在半导体鳍上的高k金属栅极结构。 在栅极结构和半导体鳍片上形成氮化物层，使用两个单独的沉积操作，首先形成非常薄的氮化物膜。 在两个氮化物膜沉积操作之间进行诸如LDD或PKT注入的植入操作。 第一氮化物膜可以是SiNx或SiCNx，并且第二氮化物膜是SiCNx，在H 3 PO 4中具有低湿蚀刻速率和稀释的HF酸。 可以将氮化物膜组合以形成低湿蚀刻速率间隔物，使得能够进行进一步的处理操作而不损坏下面的结构，而不需要形成另外的虚设间隔物。 进一步的处理操作包括外延硅/ SiGe处理序列和用低蚀刻速率间隔物完整地进行的源极/漏极注入操作。

公开(公告)号：US07996102B2

公开(公告)日：2011-08-09

申请号：US12603976

申请日：2009-10-22

Applicant: Lawrence Hendler ,  Kuo-Chin Lin ,  Svante Bjarne Wold

Inventor： Lawrence Hendler ,  Kuo-Chin Lin ,  Svante Bjarne Wold

IPC: G06F19/00

CPC classification number: G05B23/0254 ,  G05B17/02 ,  G05B2219/1112 ,  G05B2219/32187 ,  G05B2219/32201 ,  G05B2219/45031 ,  G05B2223/02 ,  Y02P90/22 ,  Y02P90/86

Abstract: A method for monitoring a manufacturing process features acquiring metrology data for semiconductor wafers at the conclusion of a final process step for the manufacturing process (“Step a”). Data is acquired for a plurality of process variables for a first process step for manufacturing semiconductor wafers (“Step b”). A first mathematical model of the first process step is created based on the metrology data and the acquired data for the plurality of process variables for the first process step (“Step c”). Steps b and c are repeated for at least a second process step for manufacturing the semiconductor wafers (“Step d”). An nth mathematical model is created based on the metrology data and the data for the plurality of process variables for each of the n process steps ('Step e“). A top level mathematical model is created based on the metrology data and the models created by steps c, d and e (”Step f'). The top level mathematical model of Step f is based on those process variables that have a substantial effect on the metrology data.

Abstract translation: 在制造过程（“步骤a”）的最终处理步骤结束时，用于监测制造过程的方法特征在于获得半导体晶片的度量数据。 对于用于制造半导体晶片的第一工艺步骤的多个工艺变量获取数据（“步骤b”）。 基于测量数据和用于第一处理步骤（“步骤c”）的多个处理变量的获取数据，创建第一处理步骤的第一数学模型。 对于用于制造半导体晶片的至少第二工艺步骤重复步骤b和c（“步骤d”）。 基于计量学数据和用于n个处理步骤（“步骤e”）中的每一个的多个处理变量的数据创建第n个数学模型。 基于测量数据和步骤c，d和e（“Step f”）创建的模型创建顶级数学模型。 步骤f的顶级数学模型基于对测量数据具有实质性影响的过程变量。