公开(公告)号：US20210367060A1

公开(公告)日：2021-11-25

申请号：US17398479

申请日：2021-08-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Haiting Wang ,  Hong Yu ,  Zhenyu Hu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L29/45 ,  H01L21/285 ,  H01L29/417

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to single fin structures and methods of manufacture. The structure includes: an active single fin structure; a plurality of dummy fin structures on opposing sides of the active single fin structure; source and drain regions formed on the active single fin structure and the dummy fin structures; recessed shallow trench isolation (STI) regions between the dummy fin structures and the active single fin structure and below a surface of the dummy fin structures; and contacts formed on the source and drain regions of the active single fin structure with a spacing of at least two dummy fin structures on opposing sides of the contacts.

公开(公告)号：US20210358865A1

公开(公告)日：2021-11-18

申请号：US16876532

申请日：2020-05-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anton Tokranov ,  Kai Sun ,  Elizabeth Strehlow ,  James Mazza ,  David Pritchard ,  Heng Yang ,  Mohamed Rabie

IPC: H01L23/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

Abstract: An illustrative device disclosed herein includes a semiconductor substrate and a FinFET transistor device positioned above the semiconductor substrate, wherein the FinFET transistor device has a single active fin structure. The device also includes an electrically inactive dummy fin structure positioned adjacent the single active fin structure, wherein the electrically inactive dummy fin structure is electrically inactive with respect to electrical operation of the FinFET transistor having the single active fin.

公开(公告)号：US20210356429A1

公开(公告)日：2021-11-18

申请号：US16874712

申请日：2020-05-15

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Jay Mody ,  Hemant Dixit

IPC: G01N27/62 ,  H01J37/285

Abstract: In APT systems and methods, a sample is analyzed by concurrently applying different types of energy to the tip of the sample, thereby causing atom evaporation from the end of the tip. Evaporated atoms are analyzed to determine chemical nature and original position information, which is used to generate a compositional profile. To ensure an accurate profile, the applied energy includes: a D.C. voltage, which lowers the critical energy level (Q) for atom evaporation; first laser pulses, which are applied to opposing first sides of the tip near the end to further lower Q and which are phase-shifted so resulting standing wave patterns of heat distribution have energy maxima that are offset and below a threshold to avoid damage to tip side surfaces; and second laser pulse(s), which is/are applied to second side(s) of the tip near the distal end to reach Q and cause atom evaporation from the end.

公开(公告)号：US11164795B2

公开(公告)日：2021-11-02

申请号：US16828273

申请日：2020-03-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Sipeng Gu ,  Judson Holt ,  Haiting Wang ,  Bangun Indajang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/08

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. First and second gate structures extend over the semiconductor body. A source/drain region is positioned laterally between the first gate structure and the second gate structure. The source/drain region includes a semiconductor layer having a first section, a second section, and a third section. A first portion of the semiconductor body is positioned between the first section of the semiconductor layer and the second section of the semiconductor layer. A second portion of the semiconductor body is positioned between the second section of the semiconductor layer and the third section of the semiconductor layer.

公开(公告)号：US11163114B2

公开(公告)日：2021-11-02

申请号：US16549466

申请日：2019-08-23

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob ,  Steven M. Shank

IPC: G02B1/00 ,  G02B6/122 ,  G02B6/125 ,  G02B6/12

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to waveguide structures with metamaterial structures and methods of manufacture. The structure includes: at least one waveguide structure; and metamaterial structures separated from the at least one waveguide structure by an insulator material, the metamaterial structures being structured to decouple the at least one waveguide structure to simultaneously reduce insertion loss and crosstalk of the at least one waveguide structure.

公开(公告)号：US20210335772A1

公开(公告)日：2021-10-28

申请号：US16857298

申请日：2020-04-24

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Wenjun LI ,  Chen PERKINS YAN ,  Tamilmani ETHIRAJAN ,  Cole E. ZEMKE

IPC: H01L27/02 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L21/8234 ,  H03F3/195

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to unitary Cascode cells with resistance and capacitance optimization, and methods of manufacture. The structure includes a common source FET (CS-FET) in a first portion of a single common semiconductor region, the CS-FET comprising a source region and a drain region, a common gate FET (CG-FET) in a second portion of the single common semiconductor region, the CG-FET comprising a source region and a drain region, and a doped connecting region of the single common semiconductor region, connecting the drain of the CS-FET and the source of the CG-FET.

公开(公告)号：US11158624B1

公开(公告)日：2021-10-26

申请号：US16857298

申请日：2020-04-24

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Wenjun Li ,  Chen Perkins Yan ,  Tamilmani Ethirajan ,  Cole E. Zemke

IPC: H01L27/08 ,  H01L27/02 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L21/8234 ,  H03F3/195 ,  H01L27/12

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to unitary Cascode cells with resistance and capacitance optimization, and methods of manufacture. The structure includes a common source FET (CS-FET) in a first portion of a single common semiconductor region, the CS-FET comprising a source region and a drain region, a common gate FET (CG-FET) in a second portion of the single common semiconductor region, the CG-FET comprising a source region and a drain region, and a doped connecting region of the single common semiconductor region, connecting the drain of the CS-FET and the source of the CG-FET.

公开(公告)号：US20210327872A1

公开(公告)日：2021-10-21

申请号：US16853137

申请日：2020-04-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Man Gu ,  Wang Zheng ,  Teng-Yin Lin ,  Haiting Wang ,  Tung-Hsing Lee

IPC: H01L27/06 ,  H01L29/78 ,  H01L49/02 ,  H01L23/66 ,  H01P3/06

Abstract: Structures including a passive device and methods of forming such structures. Multiple fins are positioned on a substrate, and an interconnect structure is positioned over the substrate. The fins contain a polycrystalline semiconductor material, and the interconnect structure includes a passive device that is positioned over the fins. The passive device may be, for example, an inductor or a transmission line.

公开(公告)号：US20210316423A1

公开(公告)日：2021-10-14

申请号：US16845629

申请日：2020-04-10

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Richard S. MCDERMOTT

IPC: B25B13/48

Abstract: The present disclosure relates to a tool and, more particularly, to cup height adjustment tool and method of use. The tool includes: a first wrench comprising a handle, a shank portion and an opening extending through the handle and the shank portion; and a second wrench having a handle and a shank portion, the shank portion of the second wrench extending through the opening of the first wrench such that a tip of the shank portion of the second wrench extends beyond the shank portion of the first wrench.

公开(公告)号：US11145348B1

公开(公告)日：2021-10-12

申请号：US16871129

申请日：2020-05-11

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Akhilesh R. Jaiswal ,  Ajey Poovannummoottil Jacob ,  Steven R. Soss

IPC: G11C14/00 ,  G11C11/16 ,  G11C7/10

Abstract: The disclosure provides a circuit structure and method for memory storage using a memory cell and magnetic random access memory (MRAM) stack. A circuit structure includes a memory cell having a first latch configured to store a digital bit, a first diode coupled to the first latch, and a first magnetic random access memory (MRAM) stack coupled to the first latch of the memory cell through the first diode. The first MRAM stack includes a first layer and a second layer each having a respective magnetic moment. The magnetic moment of the second layer is adjustable between a parallel orientation and an antiparallel orientation with respect to the magnetic moment of the first layer. Further, the magnetic anisotropy of the second layer can be modified through application of an applied voltage (VCMA effect). A spin Hall electrode is directly coupled to the first MRAM stack.