公开(公告)号：US20160276037A1

公开(公告)日：2016-09-22

申请号：US15170952

申请日：2016-06-02

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G11C16/26 ,  G06F11/10 ,  G11C29/52 ,  G11C11/56

CPC classification number: G11C16/26 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/1072 ,  G11C11/5642 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/3427 ,  G11C29/52 ,  G11C2211/5644 ,  G11C2211/5648 ,  H03M13/152

Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

公开(公告)号：US09411681B2

公开(公告)日：2016-08-09

申请号：US14957563

申请日：2015-12-02

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G11C16/00 ,  G06F11/10 ,  G11C16/26 ,  G11C29/52

CPC classification number: G11C16/26 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/1072 ,  G11C11/5642 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/3427 ,  G11C29/52 ,  G11C2211/5644 ,  G11C2211/5648 ,  H03M13/152

Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

Abstract translation: 用于读取存储在闪速存储器中的数据的方法至少包括以下步骤：控制闪速存储器对包括在闪速存储器中的多个存储器单元执行多个读取操作; 分别从存储单元获取多个位序列，其中读操作通过利用不同的控制栅极电压设置从存储单元读取预定位序的位; 以及根据比特序列的二进制数字分配特性来确定存储器单元的读出信息。

公开(公告)号：US20160148677A1

公开(公告)日：2016-05-26

申请号：US14689058

申请日：2015-04-17

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G11C11/56

CPC classification number: G11C11/5628 ,  G11C16/26 ,  G11C16/32 ,  G11C2211/5648

Abstract: A method for writing data into a flash memory, wherein the flash memory includes a plurality multi-level cells, and each of the plurality of multi-level cells is capable of storing a plurality of bits. The method includes: storing a first bit into each of the plurality of multi-level cells respectively; determining if each of the plurality of multi-level cells stores the first bit respectively; and when each of the plurality of multi-level cells stores the first bit respectively, storing a second bit into each of the plurality of multi-level cells respectively.

Abstract translation: 一种将数据写入闪速存储器的方法，其中闪速存储器包括多个多电平单元，并且多个多电平单元中的每一个能够存储多个位。 该方法包括：分别将第一位存储到多个多级信元中的每一个; 确定所述多个多电平单元中的每一个是否分别存储所述第一位; 并且当多个多电平单元中的每一个分别存储第一位时，分别将第二位存储到多个多电平单元中的每一个。

公开(公告)号：US20160110133A1

公开(公告)日：2016-04-21

申请号：US14983566

申请日：2015-12-30

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Chun-Chieh Kuo ,  Ching-Hui Lin ,  Yang-Chih Shen

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7206 ,  G11C11/5628 ,  G11C11/5642 ,  Y02D10/13

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

Abstract translation: 一种用于控制闪速存储器模块的闪存控制器包括用于接收第一数据和第二数据的通信接口; 以及处理电路，用于根据闪速存储器模块中存储的数据量来动态地控制闪存模块的数据写入模式。 如果在通信接口接收到第一数据时闪存模块中存储的数据量小于第一阈值，则处理电路控制闪存模块，使得第一数据被写入第一数据块， 每单元位数模式。 如果在通信接口接收到第二数据时闪存模块中存储的数据量大于第一阈值，则处理电路控制闪存模块，使得第二数据被写入第二数据块， 每单元位数模式。

公开(公告)号：US09268638B2

公开(公告)日：2016-02-23

申请号：US14600020

申请日：2015-01-20

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F11/10 ,  G11C16/10 ,  G11C16/26 ,  G11C11/56 ,  G11C29/52 ,  G11C16/04

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G06F11/1072 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52 ,  G11C2211/5641

Abstract: A memory control method is used for controlling a flash memory. The flash memory includes a first memory element and a second memory element. The second memory element includes multiple blocks and each block includes multiple pages. In this method, original data are written to the first memory element. Input data are obtained by reading the original data from the first memory element. The input data includes multiple input data rows. The input data rows are divided into data groups. Each input data row corresponding to each data row is written to a corresponding data page on the second memory element. A parity row corresponding to each data group is written to a data page on the second memory element. The number of data rows for each data group is smaller than the number of each block in the second memory element.

Abstract translation: 存储器控制方法用于控制闪速存储器。 闪速存储器包括第一存储器元件和第二存储器元件。 第二存储器元件包括多个块，并且每个块包括多个页。 在该方法中，将原始数据写入第一存储元件。 通过从第一存储元件读取原始数据来获得输入数据。 输入数据包括多个输入数据行。 输入数据行分为数据组。 对应于每个数据行的每个输入数据行被写入到第二存储器元件上的对应的数据页。 对应于每个数据组的奇偶校验行被写入第二存储器元件上的数据页。 每个数据组的数据行数小于第二个存储器元件中每个块的数量。

公开(公告)号：US09110824B2

公开(公告)日：2015-08-18

申请号：US13912215

申请日：2013-06-07

Applicant: Silicon Motion Inc.

Inventor： Chen-Yu Weng ,  Tsung-Chieh Yang

IPC: G06F11/10 ,  G06F12/02 ,  G11C16/34 ,  G11C29/04

CPC classification number: G06F11/1008 ,  G06F11/1048 ,  G06F12/0246 ,  G11C16/3404 ,  G11C16/3418 ,  G11C2029/0411

Abstract: A method for correcting data bit of at least a cell of a flash memory includes: determining a contributing factor of level distribution corresponding to an electric level of a first cell to generate a first determination result; and, correcting/modifying the data bit corresponding to the electric potential of the first cell according to the first determination result.

Abstract translation: 用于校正闪速存储器的至少单元的数据位的方法包括：确定与第一单元电平相对应的电平分布的贡献因子以产生第一确定结果; 以及根据第一确定结果校正/修改对应于第一单元电位的数据位。

公开(公告)号：US20150228332A1

公开(公告)日：2015-08-13

申请号：US14615435

申请日：2015-02-06

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G11C11/56

CPC classification number: G11C11/5628 ,  G11C7/02 ,  G11C7/1006 ,  G11C16/0483 ,  G11C16/10

Abstract: The present invention provides a method for writing a data into a flash memory, wherein the flash memory is a Triple-Level Cell flash memory, and each storage unit of the flash memory is implemented by a floating-gate transistor and each storage unit supports eight write voltage levels, and the method includes: adjusting the data bit by bit to generate a pseudo-random bit sequence; and writing the pseudo-random bit sequence into the flash memory with only two specific voltage levels of the eight write voltage levels.

Abstract translation: 本发明提供一种将数据写入闪速存储器的方法，其中闪速存储器是三电平单元闪速存储器，并且闪存的每个存储单元由浮栅晶体管实现，并且每个存储单元支持八 写入电压电平，并且该方法包括：逐位地调整数据以生成伪随机位序列; 以及只将八个写入电压电平的两个特定电压电平写入闪速存储器中的伪随机位序列。

公开(公告)号：US20150058661A1

公开(公告)日：2015-02-26

申请号：US14330887

申请日：2014-07-14

Applicant: Silicon Motion, Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/108 ,  G06F11/1012 ,  G06F11/1044 ,  G06F11/1076 ,  G06F2211/109 ,  G11C2029/0411

Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by a processing unit, includes at least the following steps. After a notification indicating that errors presented in a message of a sector within a RAID (Redundant Array of Independent Disk) group cannot be fixed by an error correction algorithm with a horizontal ECC (Error Correction Code) of the sector is received, addresses of the other sectors within the RAID group are determined Information is provided to a sector-decoding unit and a RAID-decoding unit, which indicates that a vertical correction procedure has been activated. Storage-unit access interfaces are directed to read content from the determined addresses of the storage unit, thereby enabling the RAID-decoding unit to recover the message of the sector by using the read content.

Abstract translation: 用于访问由处理单元执行的闪速存储器的存储单元的方法的实施例至少包括以下步骤。 在通知指示在RAID（冗余冗余阵列）组中的扇区的消息中呈现的错误不能被接收到扇区的水平ECC（纠错码）的错误校正算法固定的情况下， RAID组中的其他扇区被确定信息被提供给扇区解码单元和RAID解码单元，其指示垂直校正过程已被激活。 存储单元访问接口旨在从存储单元的确定的地址读取内容，从而使得RAID解码单元能够通过使用读取的内容来恢复扇区的消息。

公开(公告)号：US20140146605A1

公开(公告)日：2014-05-29

申请号：US13967371

申请日：2013-08-15

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G11C16/10

CPC classification number: G11C16/3431 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/34 ,  G11C16/3495 ,  G11C29/00

Abstract: A refresh method for a flash memory includes at least the following steps: performing a write operation to store an input data into a storage space in the flash memory; checking reliability of the storage space with the input data already stored therein; and when the reliability of the storage space meets a predetermined criterion, performing a refresh operation upon the storage space based on the input data. For example, the write operation stores the input data into the storage space through an initial program operation and at least one reprogram operation following the initial program operation; and the refresh operation is an additional reprogram operation applied to the storage space for programming the input data recovered from the storage space into original storage locations in the storage space.

Abstract translation: 闪存的刷新方法至少包括以下步骤：执行写入操作以将输入数据存储到闪存中的存储空间中; 使用已经存储在其中的输入数据来检查存储空间的可靠性; 并且当存储空间的可靠性满足预定标准时，基于输入数据对存储空间执行刷新操作。 例如，写入操作通过初始编程操作和在初始编程操作之后的至少一个重新编程操作将输入数据存储到存储空间中; 并且刷新操作是应用于存储空间的附加重新编程操作，用于将从存储空间恢复的输入数据编程到存储空间中的原始存储位置。

公开(公告)号：US20130305121A1

公开(公告)日：2013-11-14

申请号：US13942724

申请日：2013-07-16

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang

IPC: G06F11/18

CPC classification number: G06F11/187 ,  G06F11/1048 ,  G06F11/1479

Abstract: A method for reducing uncorrectable errors of a memory device regarding Error Correction Code (ECC) includes: performing majority vote according to data read at different times at a same address in order to generate majority vote data corresponding to the address; and checking whether the majority vote data has any uncorrectable error in order to determine whether to output the majority vote data as data of the address. For example, the method further includes: within the data read at different times at the same address, temporarily storing all of the data except for data of a last time into buffering regions/buffers, respectively, with the majority vote data being temporarily stored into a second buffering region/buffer to utilize a latest generated portion within the majority vote data to replace a latest retrieved portion within data in the second buffering region/buffer. An associated memory device and the controller thereof are further provided.

Abstract translation: 一种用于减少存储器件关于纠错码（ECC）的不可校正错误的方法，包括：根据在同一地址的不同时间读取的数据执行多数投票，以便产生对应于地址的多数投票数据; 并且检查多数投票数据是否具有任何不可校正的错误，以便确定是否输出多数投票数据作为地址的数据。 例如，该方法还包括：在相同地址的不同时间读取的数据内，分别将除最后时间的数据之外的所有数据临时存储到缓冲区域/缓冲器中，将多数投票数据临时存储到 第二缓冲区域/缓冲器，以利用多数投票数据中的最新生成部分来替换第二缓冲区域/缓冲器中的数据内的最新检索部分。 还提供了一种相关联的存储器件及其控制器。