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    Continuous time linear equalization for current-mode logic with transformer
    281.
    发明授权
    Continuous time linear equalization for current-mode logic with transformer 有权
    具有变压器电流模式逻辑的连续时间线性均衡

    公开(公告)号：US09537685B2

    公开(公告)日：2017-01-03

    申请号：US15074530

    申请日：2016-03-18

    Applicant: INPHI CORPORATION

    Inventor： Parmanand Mishra ,  Steffen Nielsen ,  Michael S. Harwood

    IPC: H04L25/03 ,  H04L25/02

    CPC classification number: H04L25/03057 ,  H03K19/094 ,  H04L25/0272 ,  H04L25/03885

    Abstract: The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide a CML that uses one or more equalization modules to apply equalization via secondary windings of transformers that are coupled, directly or indirectly, to the CML outputs. The equalization modules comprises a DAC component that generates switching signals based on control signals received from an external equalization module. The equalization module also includes switchable resistors and/or capacitors. The switching signals are used to select switchable resistors and/or capacitors. By switching resistors and/or capacitors at the equalization module, the outputs of the CML are equalized. There are other embodiments as well.

    Abstract translation: 本发明涉及数据通信系统和方法。 更具体地说，本发明的实施例提供一种使用一个或多个均衡模块通过直接或间接耦合到CML输出的变压器的次级绕组来施加均衡的CML。 均衡模块包括基于从外部均衡模块接收的控制信号产生开关信号的DAC组件。 均衡模块还包括可切换电阻器和/或电容器。 开关信号用于选择可切换电阻和/或电容器。 通过在均衡模块处切换电阻器和/或电容器，CML的输出相等。 还有其它实施例。

    Off quadrature biasing of Mach Zehnder modulator for improved OSNR performance
    282.
    发明授权
    Off quadrature biasing of Mach Zehnder modulator for improved OSNR performance 有权
    马赫曾德调制器的正交偏置关闭，以提高OSNR性能

    公开(公告)号：US09523867B2

    公开(公告)日：2016-12-20

    申请号：US15072866

    申请日：2016-03-17

    Applicant: INPHI CORPORATION

    Inventor： Radhakrishnan L. Nagarajan ,  Hari Shankar ,  Masaki Kato ,  Yang Fu

    IPC: G02B5/12 ,  G02F1/01 ,  G02F1/035 ,  G02F1/225 ,  H01S3/067 ,  H01S3/16 ,  G02F1/21

    CPC classification number: G02F1/0123 ,  G02B6/12007 ,  G02F1/0147 ,  G02F1/025 ,  G02F1/225 ,  G02F1/2255 ,  G02F2001/212 ,  G02F2202/105 ,  H01S3/06754 ,  H01S3/1608 ,  H01S5/0085 ,  H01S5/0687 ,  H01S5/4012 ,  H01S5/4087 ,  H04B10/505 ,  H04B10/50575

    Abstract: An integrated optical modulator device. The device can include a driver module coupled to an optical modulator. The optical modulator is characterized by a raised cosine transfer function. This optical modulator can be coupled to a light source and a bias control module, which is configured to apply an off-quadrature bias to the optical modulator. This bias can be accomplished by applying an inverse of the modulator transfer function to the optical modulator in order to minimize a noise variance. This compression function can result in an optimized increased top eye opening for a signal associated with the optical modulator. Furthermore, the optical modulator can be coupled to an EDFA (Erbium Doped Fiber Amplifier) that is coupled to a filter coupled an O/E (Optical-to-Electrical) receiver.

    Abstract translation: 集成光调制器装置。 该装置可以包括耦合到光调制器的驱动器模块。 光调制器的特征在于升高的余弦传递函数。 该光调制器可以耦合到光源和偏置控制模块，该偏置控制模块被配置为向光调制器施加非正交偏置。 可以通过将调制器传递函数的反相应用于光调制器来实现该偏置，以便最小化噪声方差。 该压缩功能可以导致用于与光学调制器相关联的信号的优化的增加的顶部眼睛开放。 此外，光调制器可以耦合到耦合到耦合到O / E（光 - 电）接收器的滤波器的EDFA（掺铒光纤放大器）。

    LOW POWER BUFFER WITH GAIN BOOST
    284.
    发明申请
    LOW POWER BUFFER WITH GAIN BOOST 有权
    低功耗缓冲器与增压

    公开(公告)号：US20160352372A1

    公开(公告)日：2016-12-01

    申请号：US15231449

    申请日：2016-08-08

    Applicant: INPHI CORPORATION

    Inventor： James Lawrence GORECKI ,  Han-Yuan TAN

    IPC: H04B1/16 ,  H03K5/02 ,  H03M1/12 ,  H03K3/012

    CPC classification number: H03K5/023 ,  G11C27/026 ,  H03F1/3205 ,  H03F1/3211 ,  H03F3/45183 ,  H03F3/45475 ,  H03G3/20 ,  H03K3/012 ,  H03M1/1215 ,  H03M1/124 ,  H03M3/38 ,  H04B17/21

    Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with gain boost. More specifically, some embodiments of the present disclosure are directed to a buffer with a stacked transistor configuration, wherein the first transistor receives an input signal and the second transistor receives a complement of the input signal. The first transistor is configured to generate a non-inverting response to the input signal, and the second transistor is configured to generate an inverting response to the complement of the input signal, and to generate a negative gds effect, enabling the buffer to exhibit low power and unity gain across a wide bandwidth. In other embodiments, the stacked transistor configuration can be deployed in a full differential implementation. In other embodiments, the buffer can include techniques for improving linearity, DC level shifts, capacitive input loading, and output slewing, settling, and drive capabilities.

    Abstract translation: 本公开提供了用于实现具有增益提升的低功率缓冲器的技术的详细描述。 更具体地，本公开的一些实施例涉及具有堆叠晶体管配置的缓冲器，其中第一晶体管接收输入信号，并且第二晶体管接收输入信号的补码。 第一晶体管被配置为产生对输入信号的非反相响应，并且第二晶体管被配置为产生对输入信号的补码的反相响应，并且产生负gds效应，使缓冲器显示为低 功率和单位增益在宽带宽。 在其他实施例中，堆叠晶体管配置可以部署在完全不同的实现中。 在其他实施例中，缓冲器可以包括用于改善线性度，DC电平偏移，电容性输入负载以及输出回转，稳定和驱动能力的技术。

    BUILT-IN REDUNDANCY SCHEME FOR COMMUNICATION SYSTEM ON CHIP
    285.
    发明申请
    BUILT-IN REDUNDANCY SCHEME FOR COMMUNICATION SYSTEM ON CHIP 有权
    内置通信系统冗余计划

    公开(公告)号：US20160337046A1

    公开(公告)日：2016-11-17

    申请号：US15223326

    申请日：2016-07-29

    Applicant: INPHI CORPORATION

    Inventor： Radhakrishnan L. NAGARAJAN

    IPC: H04B10/80 ,  H04J14/02 ,  H04L29/08 ,  H04B10/54 ,  H04B10/516 ,  H04B10/69 ,  H04B10/40 ,  H04B10/556

    CPC classification number: H04B10/801 ,  G02B6/00 ,  H04B10/40 ,  H04B10/5161 ,  H04B10/541 ,  H04B10/5561 ,  H04B10/69 ,  H04J14/02 ,  H04L69/324

    Abstract: In an example, the present invention includes an integrated system on chip device. The device has a redundancy block is configured to add at least redundancy bit as a function of one or more data bits associated with data for data error detection and correction data. In an example, the driver module is coupled to the signal processing blocking using a uni-directional multi-lane bus configured with N lanes, whereupon N is greater than M such that a difference between N and M represents a redundant lane or lanes. The device also has a mapping block configured to associate the M lanes to a plurality of selected laser devices for a silicon photonics device.

    Abstract translation: 在一个示例中，本发明包括集成片上系统设备。 该设备具有冗余块，被配置为至少将冗余位添加为与用于数据错误检测和校正数据的数据相关联的一个或多个数据位的函数。 在一个示例中，使用配置有N个通道的单向多通道总线将驱动器模块耦合到信号处理阻塞，因此N大于M，使得N和M之间的差异表示冗余车道或车道。 该装置还具有配置成将M通道与硅光子器件的多个选定的激光装置相关联的映射块。

    Trans-impedance amplifier with replica gain control
    287.
    发明授权
    Trans-impedance amplifier with replica gain control 有权
    具有复制增益控制的跨阻放大器

    公开(公告)号：US09473090B2

    公开(公告)日：2016-10-18

    申请号：US14550842

    申请日：2014-11-21

    Applicant: INPHI CORPORATION

    Inventor： James Lawrence Gorecki ,  Irene Quek

    IPC: H03F3/08 ,  H03F3/45 ,  H03G3/30 ,  H03G1/00 ,  H03F1/08 ,  H03F3/30

    CPC classification number: H03G3/3084 ,  H03F1/086 ,  H03F3/082 ,  H03F3/3028 ,  H03F3/45076 ,  H03F3/45179 ,  H03F2200/453 ,  H03F2203/30084 ,  H03F2203/30117 ,  H03F2203/45224 ,  H03F2203/45288 ,  H03G1/0035 ,  H04B10/2507 ,  H04B10/6911

    Abstract: This disclosure relates to the field of amplifiers for multi-level optical communication and more particularly to techniques for trans-impedance amplifiers (TIA) with gain control. The claimed embodiments address the problem of implementing a low cost TIA that exhibits high linearity, low noise, low power, and wide bandwidth. More specifically, some claims are directed to approaches for providing TIA gain control using a plurality of inverter-based replica gain control cells controlled by a feedback loop to manage the current into the amplifying output stage and thereby the TIA output voltage.

    Abstract translation: 本公开涉及用于多级光通信的放大器领域，更具体地涉及具有增益控制的跨阻抗放大器（TIA）的技术。 所要求保护的实施例解决了实现具有高线性度，低噪声，低功率和宽带宽的低成本TIA的问题。 更具体地，一些权利要求涉及用于使用由反馈环路控制的多个基于逆变器的复制增益控制单元来提供TIA增益控制的方法，以管理进入放大输出级的电流，从而管理TIA输出电压。

    MZM linear driver for silicon photonics
    288.
    发明授权
    MZM linear driver for silicon photonics 有权
    用于硅光子学的MZM线性驱动器

    公开(公告)号：US09454059B1

    公开(公告)日：2016-09-27

    申请号：US14472193

    申请日：2014-08-28

    Applicant: INPHI CORPORATION

    Inventor： Radhakrishnan L. Nagarajan

    IPC: G02F1/225 ,  G02F1/025 ,  G02F1/21 ,  G02F1/015

    CPC classification number: G02F1/0121 ,  G02F1/0123 ,  G02F1/025 ,  G02F1/225 ,  G02F1/2255 ,  G02F1/2257 ,  G02F2001/0154 ,  G02F2001/212 ,  H04B10/25 ,  H04B10/505 ,  H04L7/0075

    Abstract: The present invention includes a linear driver for Mach-Zehnder modulator (MZM) configured in a differential form with two waveguides carrying two traveling waves. Each waveguide comprises a MZM material configured with either a single segment in 3×MZM length or two split segments with one in 2×MZM length and another one in either 1× or 2×MZM length. By coupling a DC current source supplied with a modulation voltage with each segment thereof for providing electrical modulation signal overlapping with each of the two traveling waves. The modulated traveling waves in the two waveguides then are combined in one output signal by a multimode interference coupler. By properly choosing the configuration of MZM linear segments with optional length ratios, a low power consumption MZM linear driver provides either NRZ or PAM-4 modulation scheme to the input optical signals for telecommunication through silicon photonics.

    Abstract translation: 本发明包括一种以差分形式配置的马赫曾德尔调制器（MZM）的线性驱动器，其具有两个携带两个行波的波导。 每个波导包括配置有3×MZM长度的单个段或具有2×MZM长度的2个分割段的MZM材料，以及1×或2×MZM长度的另一个。 通过将提供有调制电压的DC电流源与其每个段耦合以提供与两个行波中的每一个重叠的电调制信号。 然后，两个波导中的调制行波由多模干涉耦合器组合在一个输出信号中。 通过适当选择具有可选长度比的MZM线性段的配置，低功耗MZM线性驱动器为通过硅光子学的电信输入光信号提供NRZ或PAM-4调制方案。

    High frequency delay lock loop systems
    289.
    发明授权
    High frequency delay lock loop systems 有权
    高频延迟锁定环系统

    公开(公告)号：US09438255B1

    公开(公告)日：2016-09-06

    申请号：US14815694

    申请日：2015-07-31

    Applicant: Inphi Corporation

    Inventor： Guojun Ren ,  James Gorecki ,  Karthik S. Gopalakrishnan

    IPC: H03L7/06 ,  H03L7/085

    CPC classification number: H03L7/0807 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/085

    Abstract: The present invention is directed to signal processing system and electrical circuits. According to various embodiments, a DLL system includes a delay line provides multiple output signals associated with different clock phases. The delay line may be adjusted using a pair of bias voltages. A phase detector systems generates the bias voltages using the multiple output signals from the delay line. The multiple output signals include signals associated with the first phase, the last phase, and two adjacent phases. There are other embodiments as well.

    Abstract translation: 本发明涉及信号处理系统和电路。 根据各种实施例，DLL系统包括延迟线，其提供与不同时钟相位相关联的多个输出信号。 可以使用一对偏置电压来调整延迟线。 相位检测器系统使用来自延迟线的多个输出信号产生偏置电压。 多个输出信号包括与第一阶段，最后阶段和两个相邻阶段相关联的信号。 还有其它实施例。

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