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    NON-VOLATILE RAM DISK
    25.
    发明申请
    NON-VOLATILE RAM DISK 有权
    非易失性RAM盘

    公开(公告)号：US20140013045A1

    公开(公告)日：2014-01-09

    申请号：US13993344

    申请日：2011-12-29

    申请人： James B. Crossland ,  Toby Opferman ,  Blaise Fanning

    发明人： James B. Crossland ,  Toby Opferman ,  Blaise Fanning

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0638 ,  G06F12/023 ,  G06F12/0238 ,  G06F12/0866 ,  G06F2212/202 ,  G06F2212/2024 ,  G06F2212/205 ,  G11C7/1072 ,  G11C13/0004 ,  G11C14/0036 ,  G11C14/0045

    摘要： A method and system are disclosed. In one embodiment the method includes allocating several memory locations within a phase change memory and switch (PCMS) memory to be utilized as a Random Access Memory (RAM) Disk. The RAM Disk is created for use by a software application running in a computer system. The method also includes mapping at least a portion of the allocated amount of PCMS memory to the software application address space. Finally, the method also grants the software application direct access to at least a portion of the allocated amount of the PCMS memory.

    摘要翻译： 公开了一种方法和系统。 在一个实施例中，该方法包括在相变存储器和交换机（PCMS）存储器内分配若干存储器位置，以用作随机存取存储器（RAM）盘。 RAM磁盘被创建供在计算机系统中运行的软件应用程序使用。 该方法还包括将分配的PCMS存储器的至少一部分映射到软件应用地址空间。 最后，该方法还允许软件应用直接访问PCMS存储器的分配量的至少一部分。

    METHOD AND SYSTEM FOR PROVIDING INSTANT RESPONSES TO SLEEP STATE TRANSITIONS WITH NON-VOLATILE RANDOM ACCESS MEMORY
    27.
    发明申请
    METHOD AND SYSTEM FOR PROVIDING INSTANT RESPONSES TO SLEEP STATE TRANSITIONS WITH NON-VOLATILE RANDOM ACCESS MEMORY 有权
    用非易失性随机存取存储器向休眠状态转换提供即时响应的方法和系统

    公开(公告)号：US20130283079A1

    公开(公告)日：2013-10-24

    申请号：US13976903

    申请日：2011-12-13

    申请人： Leena K. Puthiyedath ,  Raj K. Ramanujan ,  Michael Rothman ,  Blaise Fanning ,  Vincent J. Zimmer

    发明人： Leena K. Puthiyedath ,  Raj K. Ramanujan ,  Michael Rothman ,  Blaise Fanning ,  Vincent J. Zimmer

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3234 ,  G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

    摘要： A non-volatile random access memory (NVRAM) is used in a computer system to provide instant responses to sleep state transitions. The computer system includes a processor coupled to an NVRAM, which is accessible by the processor without passing through an I/O subsystem. The NVRAM is byte-rewritable and byte-erasable by the processor. In response to a request to enter a powered sleep state, the computer system converts the powered sleep state into a powered-off sleep state with system memory context stored in the NVRAM. The powered sleep state is defined as a state in which power is supplied to volatile random access memory in the computer system, and the powered-off sleep state is defined as a state in which power is removed from the volatile random access memory. In response to a wake event, the computer system resumes working state operations using the system memory context stored in the NVRAM.

    摘要翻译： 在计算机系统中使用非易失性随机存取存储器（NVRAM）来为睡眠状态转换提供即时响应。 计算机系统包括耦合到NVRAM的处理器，其可由处理器访问而不经过I / O子系统。 NVRAM是字节可重写的，可由处理器字节擦除。 响应于进入供电的睡眠状态的请求，计算机系统将动态睡眠状态转换为关闭休眠状态，并将系统存储器上下文存储在NVRAM中。 动力睡眠状态被定义为向计算机系统中的易失性随机存取存储器提供电力的状态，并且断电睡眠状态被定义为从易失性随机存取存储器去除电力的状态。 响应于唤醒事件，计算机系统使用存储在NVRAM中的系统存储器上下文来恢复工作状态操作。