Three-way proportional pressure reducing control valve
    21.
    发明申请
    Three-way proportional pressure reducing control valve 审中-公开
    三通比例减压控制阀

    公开(公告)号:US20070193639A1

    公开(公告)日:2007-08-23

    申请号:US11789861

    申请日:2007-04-26

    Abstract: A three-way proportional pressure reducing valve includes a valve body and a cylindrical valve spool. Five chambers are formed between the valve body and the cylindrical valve spool, respectively a fifth chambers, a first chamber, a second chamber, a third chamber and the fourth chamber. The first chamber connected to a high pressure inlet port P, the second chamber connected to a oil port A and the third chamber connected to a low pressure outlet port T. A first control edge being fitted between the first chamber and the second chamber, a second control edge being fitted between the second chamber and the third chamber. A first passage being located between the fifth chamber and the second chamber for connecting the second chamber to the fifth chamber, a second passage being located between the fourth chamber and the third chamber for connecting the fourth chamber to the third chamber. The present invention mainly provides a three-way proportional pressure reducing valve which can be achieved to control arbitrary pressure course change between pressure P at the constant pressure source and the oil tank at zero pressure by two damping adjustable control edges and the pressure feedback means of the chamber. The aim of the present invention is to solve the technological problem of change-over only within two limit value of zero pressure and maximum pressure and unable to control the intermediate pressure, which exists in the technology now available.

    Abstract translation: 三通比例减压阀包括阀体和圆柱形阀芯。 五个腔室分别形成在阀体和圆柱形阀芯之间,第五腔室,第一腔室,第二腔室,第三腔室和第四腔室。 连接到高压入口P的第一室,连接到油口A的第二室和连接到低压出口T的第三室。第一控制边缘装配在第一室和第二室之间, 第二控制边缘装配在第二室和第三室之间。 第一通道位于第五室和第二室之间,用于将第二室连接到第五室,第二通道位于第四室和第三室之间,用于将第四室连接到第三室。 本发明主要提供一种三通比例减压阀,其可以通过两个阻尼可调节控制边缘和压力反馈装置来控制在恒定压力源处的压力P和零压力下的油箱之间的任意压力行程变化 房间。 本发明的目的是解决仅在零压力和最大压力的两个极限值内的转换的技术问题,并且不能控制现有技术中存在的中间压力。

    Method for shallow trench isolation and shallow trench isolation structure
    22.
    发明授权
    Method for shallow trench isolation and shallow trench isolation structure 有权
    浅沟槽隔离和浅沟槽隔离结构的方法

    公开(公告)号:US06825544B1

    公开(公告)日:2004-11-30

    申请号:US09207713

    申请日:1998-12-09

    Applicant: Bo Jin

    Inventor: Bo Jin

    CPC classification number: H01L21/76235

    Abstract: Shallow trench isolation methods and corresponding structures are disclosed. According to one embodiment (900) a nitride layer (1006), having an opening (1014), is formed over a silicon substrate (1002). The portion of the substrate (1002) below the opening (1014) is oxidized to form a substrate consuming rounding oxide layer (1018). The formation of the rounding oxide layer (1018) results in rounded edges in the substrate (1002). An isotropic, or alternatively, an anisotropic rounding oxide etch removes the rounding oxide layer (1018) to expose the substrate (1002). A trench (1026) can be formed by applying a silicon etch using the nitride layer (1006) as an etch mask. The trench (1026) can be subsequently filled with a deposited trench isolation material (1030).

    Abstract translation: 公开了浅沟槽隔离方法和相应的结构。 根据一个实施例(900),在硅衬底(1002)上形成具有开口(1014)的氮化物层(1006)。 在开口(1014)下方的衬底(1002)的部分被氧化以形成消耗圆形氧化物层(1018)的衬底。 圆形氧化物层(1018)的形成导致衬底(100 2)中的圆形边缘。 各向同性,或者替代地,各向异性圆形氧化物蚀刻去除圆形氧化物层(1018)以暴露衬底(1002)。 可以通过使用氮化物层(1006)作为蚀刻掩模施加硅蚀刻来形成沟槽(1026)。 沟槽(1026)可随后用沉积的沟槽隔离材料(1030)填充。

    Reformer box with reformer tunnel including tunnel port

    公开(公告)号:US11110424B2

    公开(公告)日:2021-09-07

    申请号:US16686325

    申请日:2019-11-18

    Abstract: A top-fired reformer box is provided. The top-fired reformer box includes a burner row, a tube row, a reformer tunnel including a closed end, an open end, and a plurality of tunnel ports formed along a side wall of the reformer tunnel, the plurality of tunnel ports including a one or more tunnel port located along the side of the tunnel, and a flow resistor positioned at least one tunnel port applying a flow resistance for flue gas entering the reformer tunnel via the at least one tunnel port such that uniform flow is achieved within the reformer tunnel.

    Soft error resistant memory cell and method of manufacture
    26.
    发明授权
    Soft error resistant memory cell and method of manufacture 有权
    耐软存储单元及其制造方法

    公开(公告)号:US07355880B1

    公开(公告)日:2008-04-08

    申请号:US10823529

    申请日:2004-04-13

    CPC classification number: G11C11/4125 H01L27/11 H01L27/1104 Y10S257/903

    Abstract: A semiconductor device memory cell (100) can include a built-in capacitor for reducing a soft-error rate (SER). A memory cell (100) can include a first inverter (102) and second inverter (104) arranged in a cross-coupled configuration. A capacitor (110) can be coupled between a first storage node (106) and second storage node (108). A capacitor (110) can be a “built-in” capacitor formed with interconnect wirings utilized to connect memory cell circuit components.

    Abstract translation: 半导体器件存储单元(100)可以包括用于降低软错误率(SER)的内置电容器。 存储单元(100)可以包括以交叉耦合配置布置的第一反相器(102)和第二反相器(104)。 电容器(110)可以耦合在第一存储节点(106)和第二存储节点(108)之间。 电容器(110)可以是形成有用于连接存储器单元电路部件的互连布线的“内置”电容器。

    Proble for testing integrated circuits
    27.
    发明授权
    Proble for testing integrated circuits 有权
    测试集成电路的问题

    公开(公告)号:US07112974B1

    公开(公告)日:2006-09-26

    申请号:US10154089

    申请日:2002-05-23

    Applicant: Bo Jin Qi Gu

    Inventor: Bo Jin Qi Gu

    CPC classification number: G01R1/06711 G01R1/06716 G01R1/06738

    Abstract: In one embodiment, a probe for testing integrated circuits includes a body having a tip and a hardening material on the tip. The hardening material helps improve the hardness of the tip. The hardening material thus allows the probe to reliably penetrate a layer to make a good electrical connection with a contact point under the layer, for example. In one embodiment, an electrically conductive coating is deposited over the hardening material.

    Abstract translation: 在一个实施例中,用于测试集成电路的探针包括具有尖端的主体和尖端上的硬化材料。 硬化材料有助于提高尖端的硬度。 因此,硬化材料允许探针可靠地穿透层,以与例如层之下的接触点形成良好的电连接。 在一个实施例中,导电涂层沉积在硬化材料上。

    Method for improving dielectric polishing
    28.
    发明授权
    Method for improving dielectric polishing 有权
    改善电介质抛光的方法

    公开(公告)号:US06844237B1

    公开(公告)日:2005-01-18

    申请号:US09774323

    申请日:2001-01-31

    CPC classification number: H01L21/3083

    Abstract: According to one embodiment, a shallow trench isolation (STI) method (500) may include forming an etch mask layer over both a first and second substrate side (504). An etch mask layer over a first substrate side (506) may be patterned to form a STI etch mask, and trenches may be etched into a substrate (508). A trench dielectric layer can be formed over a first substrate side (510). An etch mask layer formed over a second substrate side can be etched (512), reducing and/or eliminating stress that may deform a substrate or otherwise adversely affect STI features. A trench dielectric may then be chemically-mechanically polished (step 514).

    Abstract translation: 根据一个实施例,浅沟槽隔离(STI)方法(500)可以包括在第一和第二衬底侧(504)上形成蚀刻掩模层。 第一衬底侧(506)上的蚀刻掩模层可以被图案化以形成STI蚀刻掩模,并且可以将沟槽蚀刻到衬底(508)中。 沟槽电介质层可以在第一衬底侧(510)上形成。 可以蚀刻形成在第二衬底侧上的蚀刻掩模层(512),减少和/或消除可能使衬底变形或以其它方式不利地影响STI特征的应力。 然后可以对沟槽电介质进行化学机械抛光(步骤514)。

    Semiconductor structure and method of making contacts and source and/or drain junctions in a semiconductor device
    30.
    发明授权
    Semiconductor structure and method of making contacts and source and/or drain junctions in a semiconductor device 有权
    在半导体器件中制造接触和源极和/或漏极结的半导体结构和方法

    公开(公告)号:US06350665B1

    公开(公告)日:2002-02-26

    申请号:US09561292

    申请日:2000-04-28

    Inventor: Bo Jin Jianmin Qiao

    Abstract: According to one embodiment (100), a method of manufacturing a semiconductor device may include forming diffusion regions in a substrate with a gate, first spacer, and second spacer as a diffusion mask (102). A second spacer may then be removed (104) prior to the formation of an interlayer dielectric. An interlayer dielectric may then be formed (106) over a gate structure and first spacer. A contact hole may then be etched through the interlayer dielectric that is self-aligned with the gate (108).

    Abstract translation: 根据一个实施例(100),制造半导体器件的方法可以包括在具有栅极,第一间隔物和第二间隔物的衬底中形成扩散区域作为扩散掩模(102)。 然后可以在形成层间电介质之前去除第二间隔物(104)。 然后可以在栅极结构和第一间隔物上形成(106)层间电介质。 然后可以通过与栅极(108)自对准的层间电介质蚀刻接触孔。

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