Abstract:
A three-way proportional pressure reducing valve includes a valve body and a cylindrical valve spool. Five chambers are formed between the valve body and the cylindrical valve spool, respectively a fifth chambers, a first chamber, a second chamber, a third chamber and the fourth chamber. The first chamber connected to a high pressure inlet port P, the second chamber connected to a oil port A and the third chamber connected to a low pressure outlet port T. A first control edge being fitted between the first chamber and the second chamber, a second control edge being fitted between the second chamber and the third chamber. A first passage being located between the fifth chamber and the second chamber for connecting the second chamber to the fifth chamber, a second passage being located between the fourth chamber and the third chamber for connecting the fourth chamber to the third chamber. The present invention mainly provides a three-way proportional pressure reducing valve which can be achieved to control arbitrary pressure course change between pressure P at the constant pressure source and the oil tank at zero pressure by two damping adjustable control edges and the pressure feedback means of the chamber. The aim of the present invention is to solve the technological problem of change-over only within two limit value of zero pressure and maximum pressure and unable to control the intermediate pressure, which exists in the technology now available.
Abstract:
Shallow trench isolation methods and corresponding structures are disclosed. According to one embodiment (900) a nitride layer (1006), having an opening (1014), is formed over a silicon substrate (1002). The portion of the substrate (1002) below the opening (1014) is oxidized to form a substrate consuming rounding oxide layer (1018). The formation of the rounding oxide layer (1018) results in rounded edges in the substrate (1002). An isotropic, or alternatively, an anisotropic rounding oxide etch removes the rounding oxide layer (1018) to expose the substrate (1002). A trench (1026) can be formed by applying a silicon etch using the nitride layer (1006) as an etch mask. The trench (1026) can be subsequently filled with a deposited trench isolation material (1030).
Abstract:
A top-fired reformer box is provided. The top-fired reformer box includes a burner row, a tube row, a reformer tunnel including a closed end, an open end, and a plurality of tunnel ports formed along a side wall of the reformer tunnel, the plurality of tunnel ports including a one or more tunnel port located along the side of the tunnel, and a flow resistor positioned at least one tunnel port applying a flow resistance for flue gas entering the reformer tunnel via the at least one tunnel port such that uniform flow is achieved within the reformer tunnel.
Abstract:
A tubular reactor for producing a product mixture in a tubular reactor where the tubular reactor comprises an internal catalytic insert with cup-shaped structures having orifices for forming fluid jets for impinging the fluid on the tube wall. Jet impingement is used to improve heat transfer between the fluid in the tube and the tube wall in a non-adiabatic reactor. The tubular reactor and method may be used for endothermic reactions such as steam methane reforming and for exothermic reactions such as methanation.
Abstract:
A tubular reactor and method for producing a product mixture in a tubular reactor where the tubular reactor comprises an internal catalytic insert having orifices for forming fluid jets for impinging the fluid on the tube wall. Jet impingement is used to improve heat transfer between the fluid in the tube and the tube wall in a non-adiabatic reactor. The tubular reactor and method may be used for endothermic reactions such as steam methane reforming and for exothermic reactions such as methanation.
Abstract:
A semiconductor device memory cell (100) can include a built-in capacitor for reducing a soft-error rate (SER). A memory cell (100) can include a first inverter (102) and second inverter (104) arranged in a cross-coupled configuration. A capacitor (110) can be coupled between a first storage node (106) and second storage node (108). A capacitor (110) can be a “built-in” capacitor formed with interconnect wirings utilized to connect memory cell circuit components.
Abstract:
In one embodiment, a probe for testing integrated circuits includes a body having a tip and a hardening material on the tip. The hardening material helps improve the hardness of the tip. The hardening material thus allows the probe to reliably penetrate a layer to make a good electrical connection with a contact point under the layer, for example. In one embodiment, an electrically conductive coating is deposited over the hardening material.
Abstract:
According to one embodiment, a shallow trench isolation (STI) method (500) may include forming an etch mask layer over both a first and second substrate side (504). An etch mask layer over a first substrate side (506) may be patterned to form a STI etch mask, and trenches may be etched into a substrate (508). A trench dielectric layer can be formed over a first substrate side (510). An etch mask layer formed over a second substrate side can be etched (512), reducing and/or eliminating stress that may deform a substrate or otherwise adversely affect STI features. A trench dielectric may then be chemically-mechanically polished (step 514).
Abstract:
According to one embodiment (300), a method of forming a self-aligned contact can include forming adjacent conducting structures with sidewalls (302). A first insulating layer may then be formed without first forming a liner (304), such as a liner that is conventionally formed to protect underlying conducting structures and/or a substrate. A contact hole may then be etched between adjacent conducting structures (306). Contact structures may then be formed (308).
Abstract:
According to one embodiment (100), a method of manufacturing a semiconductor device may include forming diffusion regions in a substrate with a gate, first spacer, and second spacer as a diffusion mask (102). A second spacer may then be removed (104) prior to the formation of an interlayer dielectric. An interlayer dielectric may then be formed (106) over a gate structure and first spacer. A contact hole may then be etched through the interlayer dielectric that is self-aligned with the gate (108).