公开(公告)号：US20110316294A1

公开(公告)日：2011-12-29

申请号：US12954049

申请日：2010-11-24

申请人： Chul Kim ,  Byung Sun Kim ,  Jae Hwan Jung

发明人： Chul Kim ,  Byung Sun Kim ,  Jae Hwan Jung

IPC分类号： E05B15/02

CPC分类号： B62D25/04 ,  Y10T292/68

摘要： The present invention relates to a door striker unit for a vehicle. The door striker unit for a vehicle includes a retainer connected to a rear side of the vehicle's side outer panel, a engaging plate connected to a rear surface of the retainer, and a striker connected to the engaging plate and positioned on a front side of the vehicle's side outer panel, wherein the engaging plate includes a welding portion welded to the retainer, an engaging portion having an integral bolt engaging portion for connection with the striker, and a connecting portion integrally connecting the welding portion and the engaging portion, wherein the connecting portion comprises a protruding curved portion.

摘要翻译： 本发明涉及一种用于车辆的门撞击器单元。 用于车辆的车门撞击装置包括连接到车辆侧外板的后侧的保持器，连接到保持器的后表面的接合板和连接到接合板并且位于车辆侧面外侧的前侧上的撞针 车辆侧外板，其中所述接合板包括焊接到所述保持器的焊接部分，具有用于与所述撞针连接的一体的螺栓接合部分的接合部分和将所述焊接部分与所述接合部分整体连接的连接部分，其中所述连接 部分包括突出的弯曲部分。

公开(公告)号：US20090020844A1

公开(公告)日：2009-01-22

申请号：US12219336

申请日：2008-07-21

申请人： Myoung-kyu Park ,  Byung-sun Kim ,  Tae-jung Lee ,  Kee-in Bang

发明人： Myoung-kyu Park ,  Byung-sun Kim ,  Tae-jung Lee ,  Kee-in Bang

IPC分类号： H01L27/06

CPC分类号： H01L27/0814 ,  H01L27/0255

摘要： Semiconductor device having an on-chip type electrostatic discharge (ESD) protection circuit and a method of manufacturing the same are provided. The on-chip type ESD protection circuit may include a first junction diode having a first conductive type region contacting a second conductive type region in a semiconductor substrate, and a first schottky diode having a metallic material layer arranged on and contacting the first conductive type region of the semiconductor substrate.

摘要翻译： 提供具有片上型静电放电（ESD）保护电路的半导体器件及其制造方法。 片上型ESD保护电路可以包括具有与半导体衬底中的第二导电类型区域接触的第一导电类型区域的第一结二极管和具有布置在第一导电类型区域上并与第一导电类型区域接触的金属材料层的第一肖特基二极管 的半导体衬底。

公开(公告)号：US07276862B2

公开(公告)日：2007-10-02

申请号：US11317708

申请日：2005-12-22

申请人： Byung-Sun Kim ,  Kyung-Soo Seok

发明人： Byung-Sun Kim ,  Kyung-Soo Seok

IPC分类号： G05F1/00

CPC分类号： H05B41/288 ,  Y10S315/04 ,  Y10S315/05

摘要： A stabilizer circuit for a high-voltage discharge lamp is provided. The stabilizer comprises an electromagnetic interference (EMI) filter; a rectifying unit; a power factor correction (PFC) circuit; a buck converter; a commutator; an igniter; a high-voltage discharge lamp; a current detector; a voltage detector; an igniter voltage controller for receiving the voltage output from the igniter and controlling the voltage when abnormality in the high-voltage discharge lamp occurs.

摘要翻译： 提供了一种用于高压放电灯的稳定电路。 稳定器包括电磁干扰（EMI）滤波器; 整流单元 功率因数校正（PFC）电路; 降压转换器; 换向器 点火器 高压放电灯; 电流检测器; 电压检测器; 点火器电压控制器，用于接收从点火器输出的电压并且在高压放电灯中发生异常时控制电压。

公开(公告)号：US07271059B2

公开(公告)日：2007-09-18

申请号：US11048845

申请日：2005-02-03

申请人： Sang-Soo Kim ,  Byung-Sun Kim

发明人： Sang-Soo Kim ,  Byung-Sun Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

摘要： A method of fabricating a semiconductor device having a non-volatile memory cell includes forming an insulation layer as an uppermost/outermost portion of the memory cell to enhance the charge retention capability of the memory cell. The insulation layer is formed after the gate structure and integrate dielectric of the non-volatile memory cell, and a gate of a logic transistor are formed. The insulation layer thus enhances the function of the intergrate dielectric. Subsequently, a conductive layer is formed on the substrate including over the gate of the logic transistor. A silicide layer is then formed on the gate of the logic transistor and on the substrate adjacent opposite sides of the gate. The insulation layer thus also serves prevent the formation of a silicide layer on the non-volatile memory cell.

摘要翻译： 制造具有非易失性存储单元的半导体器件的方法包括形成作为存储单元的最上部/最外部的绝缘层，以提高存储单元的电荷保持能力。 在栅极结构之后形成绝缘层并且整合非易失性存储单元的电介质，并且形成逻辑晶体管的栅极。 因此，绝缘层增强了集成电介质的功能。 随后，在包括在逻辑晶体管的栅极上的衬底上形成导电层。 然后在逻辑晶体管的栅极上和邻近栅极的相对侧的衬底上形成硅化物层。 因此，绝缘层也用于防止在非易失性存储单元上形成硅化物层。

公开(公告)号：US20070145467A1

公开(公告)日：2007-06-28

申请号：US11538239

申请日：2006-10-03

申请人： Geun-sook Park ,  Byung-sun Kim ,  Sang-bae Yi ,  Ho-ik Hwang ,  Myung-hee Kim ,  Hye-young Park

发明人： Geun-sook Park ,  Byung-sun Kim ,  Sang-bae Yi ,  Ho-ik Hwang ,  Myung-hee Kim ,  Hye-young Park

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L29/66825

摘要： An EEPROM includes a semiconductor substrate and a device isolation region defining first, second and third active regions in the semiconductor substrate. The EEPROM also includes at least one first insulation region in at least one first trench in the first active region. A floating gate insulation layer is disposed on the at least one first insulation region and the first, second and third active regions and a floating gate conduction layer is disposed on the floating gate insulation layer. Impurity-containing regions may be disposed in each of the first, second and third active regions at respective sides of the floating gate conduction layer. The floating gate insulation layer may include at least one thinned portion proximate the at least one first insulation region, which may aid Fowler-Nordheim tunneling at this site.

摘要翻译： EEPROM包括半导体衬底和限定半导体衬底中的第一，第二和第三有源区的器件隔离区。 EEPROM还包括在第一有源区域中的至少一个第一沟槽中的至少一个第一绝缘区域。 浮置栅极绝缘层设置在至少一个第一绝缘区域和第一，第二和第三有源区域上，并且浮置栅极导电层设置在浮置栅极绝缘层上。 含杂质的区域可以布置在浮置栅极导电层的相应侧的第一，第二和第三有源区域的每一个中。 浮栅绝缘层可以包括靠近至少一个第一绝缘区域的至少一个变薄部分，这可以有助于在该部位的Fowler-Nordheim隧道。

公开(公告)号：US20070025174A1

公开(公告)日：2007-02-01

申请号：US11470826

申请日：2006-09-07

申请人： Tae-Jung LEE ,  Byung-Sun KIM ,  Joon-Hung LEE

发明人： Tae-Jung LEE ,  Byung-Sun KIM ,  Joon-Hung LEE

IPC分类号： G11C8/00

CPC分类号： H01L27/1104 ,  G09G3/3611 ,  G11C7/02 ,  G11C8/16 ,  G11C11/4125 ,  H01L27/11

摘要： A dual port semiconductor memory device, including PMOS scan transistors, is provided. The dual port semiconductor memory device includes two PMOS transistors, two NMOS pull-down transistors, two NMOS pass transistors, and a PMOS scan transistor. The scan transistor being PMOS, noise margins can be improved. In addition, these seven transistors are arranged in two n-wells and 2 p-wells, while n-wells and p-wells are arranged in series and in alternating fashion. Therefore, the length of a memory cell along the minor axis of the memory cell is relatively short. This memory cell layout helps shorten the length of a bit line by arranging a pair of bitlines in parallel with well boundaries, i.e., in the direction of the short axis of the memory cell, and makes it possible to prevent crosstalk between a bitline and a complementary bitline by arranging conductive lines between the bitline and the complementary bitline.

摘要翻译： 提供了包括PMOS扫描晶体管的双端口半导体存储器件。 双端口半导体存储器件包括两个PMOS晶体管，两个NMOS下拉晶体管，两个NMOS传输晶体管和PMOS扫描晶体管。 作为PMOS的扫描晶体管，可以提高噪声容限。 此外，这七个晶体管排列在两个n阱和2个p阱中，而n阱和p阱以串联和交替的方式排列。 因此，沿着存储单元的短轴的存储单元的长度相对较短。 该存储单元布局通过将一对位线与阱边界并排布置，即在存储单元的短轴方向上有助于缩短位线的长度，并且可以防止位线与位线之间的串扰 通过在位线和互补位线之间布置导线来补充位线。

公开(公告)号：US07120080B2

公开(公告)日：2006-10-10

申请号：US10751178

申请日：2004-01-02

申请人： Tae-Jung Lee ,  Byung-Sun Kim ,  Joon-Hyung Lee

发明人： Tae-Jung Lee ,  Byung-Sun Kim ,  Joon-Hyung Lee

IPC分类号： G11C8/00 ,  G11C5/06 ,  G11C11/00 ,  G06F12/00 ,  G06F13/28

CPC分类号： H01L27/1104 ,  G09G3/3611 ,  G11C7/02 ,  G11C8/16 ,  G11C11/4125 ,  H01L27/11

摘要： A dual port semiconductor memory device, including PMOS scan transistors, is provided. The dual port semiconductor memory device includes two PMOS transistors, two NMOS pull-down transistors, two NMOS pass transistors, and a PMOS scan transistor. The scan transistor being PMOS, noise margins can be improved. In addition, these seven transistors are arranged in two n-wells and 2 p-wells, while n-wells and p-wells are arranged in series and in alternating fashion. Therefore, the length of a memory cell along the minor axis of the memory cell is relatively short. This memory cell layout helps shorten the length of a bit line by arranging a pair of bitlines in parallel with well boundaries, i.e., in the direction of the short axis of the memory cell, and makes it possible to prevent crosstalk between a bitline and a complementary bitline by arranging conductive lines between the bitline and the complementary bitline.

摘要翻译： 提供了包括PMOS扫描晶体管的双端口半导体存储器件。 双端口半导体存储器件包括两个PMOS晶体管，两个NMOS下拉晶体管，两个NMOS传输晶体管和PMOS扫描晶体管。 作为PMOS的扫描晶体管，可以提高噪声容限。 此外，这七个晶体管排列在两个n阱和2个p阱中，而n阱和p阱以串联和交替的方式排列。 因此，沿着存储单元的短轴的存储单元的长度相对较短。 该存储单元布局通过将一对位线与阱边界并排布置，即在存储单元的短轴方向上有助于缩短位线的长度，并且可以防止位线与位线之间的串扰 通过在位线和互补位线之间布置导线来补充位线。

公开(公告)号：US06995447B2

公开(公告)日：2006-02-07

申请号：US10810285

申请日：2004-03-26

申请人： Tae-jung Lee ,  Byung-sun Kim ,  Myoung-hwan Oh ,  Seung-han Yoo ,  Myung-sun Shin ,  Sang-wook Park

发明人： Tae-jung Lee ,  Byung-sun Kim ,  Myoung-hwan Oh ,  Seung-han Yoo ,  Myung-sun Shin ,  Sang-wook Park

IPC分类号： H10L29/00 ,  H10L27/01 ,  H10L29/76 ,  H10L29/40

CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L21/76283 ,  H01L29/78615 ,  H01L29/78636

摘要： A silicon-on-insulator (SOI) device and a method for manufacturing the same includes a substrate, which includes a base layer, a buried oxide layer, and a semiconductor layer, and an isolation layer which is formed in a trench that defines an active region on the semiconductor layer. The trench comprises a first region having a depth smaller than the thickness of the semiconductor layer and a second region having a depth as much as the thickness of the semiconductor layer. The isolation layer includes an oxide layer and a nitride liner that are sequentially formed along the surface of the trench and a dielectric layer that fills the trench.

公开(公告)号：US20050173753A1

公开(公告)日：2005-08-11

申请号：US11048845

申请日：2005-02-03

申请人： Sang-Soo Kim ,  Byung-Sun Kim

发明人： Sang-Soo Kim ,  Byung-Sun Kim

IPC分类号： H01L29/78 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11546

摘要： A method of fabricating a semiconductor device having a non-volatile memory cell includes forming an insulation layer as an uppermost/outermost portion of the memory cell to enhance the charge retention capability of the memory cell. The insulation layer is formed after the gate structure and integrate dielectric of the non-volatile memory cell, and a gate of a logic transistor are formed. The insulation layer thus enhances the function of the intergate dielectric. Subsequently, a conductive layer is formed on the substrate including over the gate of the logic transistor. A silicide layer is then formed on the gate of the logic transistor and on the substrate adjacent opposite sides of the gate. The insulation layer thus also serves prevent the formation of a silicide layer on the non-volatile memory cell.

摘要翻译： 制造具有非易失性存储单元的半导体器件的方法包括形成作为存储单元的最上部/最外部的绝缘层，以提高存储单元的电荷保持能力。 在栅极结构之后形成绝缘层并且整合非易失性存储单元的电介质，并且形成逻辑晶体管的栅极。 因此，绝缘层增强了隔间电介质的功能。 随后，在包括在逻辑晶体管的栅极上的衬底上形成导电层。 然后在逻辑晶体管的栅极上和邻近栅极的相对侧的衬底上形成硅化物层。 因此，绝缘层也用于防止在非易失性存储单元上形成硅化物层。

公开(公告)号：US06689648B2

公开(公告)日：2004-02-10

申请号：US10134798

申请日：2002-04-29

申请人： Young-Gun Ko ,  Byung-Sun Kim ,  Young-Wug Kim

发明人： Young-Gun Ko ,  Byung-Sun Kim ,  Young-Wug Kim

IPC分类号： H01L2100

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： The present invention relates to an SOI semiconductor device and a method for fabricating an SOI semiconductor device, in which the portions formed with silicide layers are laterally restricted by spacers to a predetermined range in the diffusion regions to be used for diodes or well resistors. In this manner, it is possible to fix the length of distance between the sides of a silicide layer and a diffusion region, greater than that available in the prior art techniques, thereby minimizing power leakage at the sides of the diffusion regions. In the SOI semiconductor device thus constructed, the diffusion regions to be used for diodes (or well resistors) are constructed with spacers in a double junction structure of different density of impurity layers (for instance, a P− or N− layer respectively surrounds a P+ or N+ layer), in other words, only onto a high density of impurity layer, the P+ or N+ layer, or in a single junction structure in which the spacers restrict a range of space for forming the silicide layer in the diffusion region.

摘要翻译： SOI半导体器件及SOI半导体器件的制造方法本发明涉及一种SOI半导体器件的制造方法，其中由硅化物层形成的部分在隔离层中被横向限制在用于二极管或阱电阻器的扩散区域中的预定范围内。 以这种方式，可以固定硅化物层和扩散区域的侧面之间的距离长度，大于现有技术中可用的距离，从而最小化扩散区域侧面的功率泄漏。 在如此构造的SOI半导体器件中，用于二极管（或阱电阻器）的扩散区域由具有不同密度杂质层的双结结构中的间隔物构成（例如，P-或N-层分别围绕 P +或N +层），换句话说，仅在高密度的杂​​质层，P +或N +层上，或在单结结构中，其中间隔物限制在扩散区域中形成硅化物层的空间范围。