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    INTEGRATED CIRCUITS FOR PROVIDING CLOCK PERIODS AND OPERATING METHODS THEREOF
    21.
    发明申请
    INTEGRATED CIRCUITS FOR PROVIDING CLOCK PERIODS AND OPERATING METHODS THEREOF 有权
    用于提供时钟周期的集成电路及其操作方法

    公开(公告)号：US20120026820A1

    公开(公告)日：2012-02-02

    申请号：US12844204

    申请日：2010-07-27

    Applicant: Chiang PU ,  Ming-Chieh HUANG ,  Chan-Hong CHERN

    Inventor： Chiang PU ,  Ming-Chieh HUANG ,  Chan-Hong CHERN

    IPC: G11C7/00 ,  G05F1/10

    CPC classification number: G05F1/10 ,  G11C7/22 ,  G11C7/222 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40626 ,  G11C2211/4065

    Abstract: An integrated circuit includes a capacitor. A switch is electrically coupled with the capacitor in a parallel fashion. A comparator includes a first input node, a second input node, and an output node. The second input node is electrically coupled with a first plate of the capacitor. The output node is electrically coupled with the switch. A transistor is electrically coupled with a second plate of the capacitor. A circuit is electrically coupled with a gate of the transistor. The circuit is configured to provide a bias voltage to the gate of the transistor so as to control a current that is supplied to charge the capacitor.

    Abstract translation: 集成电路包括电容器。 开关以并联方式与电容器电耦合。 比较器包括第一输入节点，第二输入节点和输出节点。 第二输入节点与电容器的第一板电耦合。 输出节点与开关电耦合。 晶体管与电容器的第二板电耦合。 电路与晶体管的栅极电耦合。 电路被配置为向晶体管的栅极提供偏置电压，以便控制供给电容器充电的电流。

    VOLTAGE REGULATORS, MEMORY CIRCUITS, AND OPERATING METHODS THEREOF
    22.
    发明申请
    VOLTAGE REGULATORS, MEMORY CIRCUITS, AND OPERATING METHODS THEREOF 有权
    电压调节器，存储器电路及其操作方法

    公开(公告)号：US20110310690A1

    公开(公告)日：2011-12-22

    申请号：US12820712

    申请日：2010-06-22

    Applicant: Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Tien Chun YANG ,  Chih-Chang LIN ,  Yuwen SWEI

    Inventor： Ming-Chieh HUANG ,  Chan-Hong CHERN ,  Tien Chun YANG ,  Chih-Chang LIN ,  Yuwen SWEI

    IPC: G11C5/14

    CPC classification number: G11C11/4074 ,  G11C5/147

    Abstract: A voltage regulator includes an output stage electrically coupled with an output end of the voltage regulator. The output stage includes at least one transistor having a bulk and a drain. At least one back-bias circuit is electrically coupled with the bulk of the at least one transistor. The at least one back-bias circuit is configured to provide a bulk voltage, such that the bulk and the drain of the at least one transistor are reverse biased during a standby mode of a memory array that is electrically coupled with the voltage regulator.

    Abstract translation: 电压调节器包括与电压调节器的输出端电耦合的输出级。 输出级包括具有体积和漏极的至少一个晶体管。 至少一个背偏置电路与所述至少一个晶体管的主体电耦合。 至少一个背偏置电路被配置为提供体电压，使得在与电压调节器电耦合的存储器阵列的待机模式期间，至少一个晶体管的体积和漏极被反向偏置。

    INTEGRATED CIRCUITS HAVING DUMMY GATE ELECTRODES AND METHODS OF FORMING THE SAME
    23.
    发明申请
    INTEGRATED CIRCUITS HAVING DUMMY GATE ELECTRODES AND METHODS OF FORMING THE SAME 有权
    具有双门电极的集成电路及其形成方法

    公开(公告)号：US20110298059A1

    公开(公告)日：2011-12-08

    申请号：US12795144

    申请日：2010-06-07

    Applicant: Mei-Hui HUANG ,  Chan-Hong CHERN

    Inventor： Mei-Hui HUANG ,  Chan-Hong CHERN

    IPC: H01L27/088 ,  H01L21/336

    CPC classification number: H01L27/088 ,  H01L21/823425 ,  H01L21/823437 ,  H01L27/0207 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/42372 ,  H01L29/66545

    Abstract: An integrated circuit includes at least one first gate electrode of at least one active transistor. At least one first dummy gate electrode is disposed adjacent to a first side edge of the at least one first gate electrode. At least one second dummy gate electrode is disposed adjacent to a second side edge of the at least one first gate electrode. The second side edge is opposite to the first side edge. At least one guard ring is disposed around the at least one first gate electrode, the at least one first dummy gate electrode, and the at least one second dummy gate electrode. An ion implantation layer of the at least one guard ring substantially touches at least one of the at least one first dummy gate electrode and the at least one second dummy gate electrode.

    Abstract translation: 集成电路包括至少一个有源晶体管的第一栅电极。 至少一个第一虚拟栅电极设置成与所述至少一个第一栅电极的第一侧边缘相邻。 至少一个第二伪栅电极设置成与所述至少一个第一栅电极的第二侧边相邻。 第二侧边缘与第一侧边缘相对。 至少一个保护环布置在所述至少一个第一栅电极，所述至少一个第一虚拟栅极电极和所述至少一个第二虚拟栅电极周围。 所述至少一个保护环的离子注入层基本上接触所述至少一个第一伪栅极电极和所述至少一个第二虚设栅极电极中的至少一个。

    Decision feedback equalizer having programmable taps
    28.
    发明授权
    Decision feedback equalizer having programmable taps 有权
    具有可编程抽头的判决反馈均衡器

    公开(公告)号：US08971395B2

    公开(公告)日：2015-03-03

    申请号：US13293513

    申请日：2011-11-10

    Applicant: Ming-Chieh Huang ,  Jing Jing Chen ,  Chan-Hong Chern ,  Tao Wen Chung ,  Chih-Chang Lin ,  Yuwen Swei

    Inventor： Ming-Chieh Huang ,  Jing Jing Chen ,  Chan-Hong Chern ,  Tao Wen Chung ,  Chih-Chang Lin ,  Yuwen Swei

    IPC: H03H7/30 ,  H04L25/03

    CPC classification number: H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03566 ,  H04L2025/03617 ,  H04L2025/03687

    Abstract: A Decision Feedback Equalizer (DFE) with programmable taps includes a summer configured to receive a DFE input signal. Delay elements are coupled to the summer. The delay elements are connected in series. Each delay element provides a respective delayed signal of an input signal to the delay element. A weight generator is configured to provide tap weights. The DFE is configured to multiply each tap weight to the respective delayed signal from the respective delay element to provide tap outputs. Each tap output is selectively enabled to be added to the summer or disabled based on a first comparison of a first threshold value and each impulse response or each tap weight corresponding to the respective tap output, where the impulse response is the DFE input signal in response to a pulse signal transmitted through a channel.

    Abstract translation: 具有可编程抽头的判决反馈均衡器（DFE）包括一个加法器，用于接收DFE输入信号。 延迟元素与夏天相结合。 延迟元件串联连接。 每个延迟元件向延迟元件提供输入信号的相应延迟信号。 重量发生器被配置成提供抽头重量。 DFE被配置为将每个抽头权重乘以来自相应延迟元件的相应延迟信号以提供抽头输出。 基于第一阈值和对应于各抽头输出的每个脉冲响应或每个抽头权重的第一比较，每个抽头输出被选择性地被加到加法器或禁止中，其中脉冲响应是响应中的DFE输入信号 通过通道传输的脉冲信号。

    Phase locked loop calibration
    29.
    发明授权
    Phase locked loop calibration 有权
    锁相环校准

    公开(公告)号：US08698566B2

    公开(公告)日：2014-04-15

    申请号：US13252498

    申请日：2011-10-04

    Applicant: Chan-Hong Chern ,  Ming-Chieh Huang ,  Tao Wen Chung ,  Chih-Chang Lin ,  Fu-Lung Hsueh ,  Yuwen Swei

    Inventor： Chan-Hong Chern ,  Ming-Chieh Huang ,  Tao Wen Chung ,  Chih-Chang Lin ,  Fu-Lung Hsueh ,  Yuwen Swei

    IPC: H03L7/085 ,  H03L7/10 ,  H03B5/12

    CPC classification number: H03L7/102 ,  H03L7/099 ,  H03L2207/06

    Abstract: An inductor-capacitor phase locked loop (LCPLL) includes an inductor-capacitor voltage controlled oscillator (LCVCO) that provides an output frequency. A calibration circuit includes two comparators and provides a coarse tune signal to the LCVCO. The two comparators respectively compare the loop filter signal with a first reference voltage and a second reference voltage that is higher than the first reference voltage to supply a first and second comparator output, respectively. The calibration circuit is capable of adjusting the coarse tune signal continuously in voltage values and adjusts the coarse tune signal based on the two comparator outputs. A loop filter provides a loop filter signal to the calibration circuit and a fine tune signal to the LCVCO. A coarse tune frequency range is greater than a fine tune frequency range.

    Abstract translation: 电感 - 电容器锁相环（LCPLL）包括提供输出频率的电感 - 电容压控振荡器（LCVCO）。 校准电路包括两个比较器，并向LCVCO提供粗调信号。 两个比较器分别将环路滤波器信号与第一参考电压和高于第一参考电压的第二参考电压进行比较，以分别提供第一和第二比较器输出。 校准电路能够在电压值中连续调整粗调信号，并根据两个比较器输出调整粗调信号。 环路滤波器向校准电路提供环路滤波器信号，并向LCVCO提供微调信号。 粗调频率范围大于微调频率范围。

    Slicer and method of operating the same
    30.
    发明授权
    Slicer and method of operating the same 有权
    切片机及其操作方法

    公开(公告)号：US08643422B1

    公开(公告)日：2014-02-04

    申请号：US13547396

    申请日：2012-07-12

    Applicant: Ming-Chieh Huang ,  Chan-Hong Chern ,  Tao Wen Chung ,  Chih-Chang Lin ,  Tsung-Ching Huang ,  Derek C. Tao

    Inventor： Ming-Chieh Huang ,  Chan-Hong Chern ,  Tao Wen Chung ,  Chih-Chang Lin ,  Tsung-Ching Huang ,  Derek C. Tao

    IPC: H03K3/356

    CPC classification number: H03K5/08 ,  H03K3/356139 ,  H04L27/01

    Abstract: This description relates to a slicer including a first latch. The first latch includes an evaluating transistor configured to receive a first clock signal and a developing transistor configured to receive a second clock signal. The first clock signal is different from the second clock signal. The first latch includes first and second input transistors configured to receive first and second complementary inputs. The first latch includes at least one pre-charging transistor configured to receive a third clock signal. The first latch further at least one cross-latched pair of transistors, the at least one cross-latched transistor pair connected between the evaluating transistor and the first and second output nodes. The slicer includes a second latch connected to the first and second output nodes and to a third output node. The slicer includes a buffer connected to the third output node and configured to generate a final output signal.

    Abstract translation: 该描述涉及包括第一锁存器的限幅器。 第一锁存器包括被配置为接收第一时钟信号的评估晶体管和被配置为接收第二时钟信号的显影晶体管。 第一时钟信号与第二时钟信号不同。 第一锁存器包括被配置为接收第一和第二互补输入的第一和第二输入晶体管。 第一锁存器包括配置成接收第三时钟信号的至少一个预充电晶体管。 第一锁存器还包括至少一个交叉锁存晶体管对，该至少一个交叉锁存晶体管对连接在评估晶体管与第一和第二输出节点之间。 切片器包括连接到第一和第二输出节点和第三输出节点的第二锁存器。 切片器包括连接到第三输出节点并被配置为产生最终输出信号的缓冲器。

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