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公开(公告)号：US5434093A
公开(公告)日：1995-07-18
申请号：US288332
申请日：1994-08-10
申请人： Robert S. Chau , Chan-Hong Chern , Shahriar S. Ahmed , Robert F. Hainsey , Robert J. Stoner , Todd E. Wilke , Leopoldo D. Yau
发明人： Robert S. Chau , Chan-Hong Chern , Shahriar S. Ahmed , Robert F. Hainsey , Robert J. Stoner , Todd E. Wilke , Leopoldo D. Yau
IPC分类号： H01L21/336 , H01L29/08 , H01L29/10 , H01L29/423 , H01L21/265
CPC分类号： H01L29/66583 , H01L29/0847 , H01L29/1033 , H01L29/41783 , H01L29/42376 , H01L29/66553 , H01L29/66628 , H01L29/66537
摘要： A method for forming narrow length transistors by forming a trench in a first layer over a semiconductor substrate. Spacers are then formed within the trench and a gate dielectric is formed between the spacers at the bottom of the trench on the semiconductor substrate. The trench is then filled with a gate electrode material which is chemically-mechanically polished back to isolate the gate electrode material within the trench, and the first layer is removed leaving the gate dielectric, gate electrode and spacers behind.
摘要翻译： 一种通过在半导体衬底上的第一层中形成沟槽来形成窄长度晶体管的方法。 然后在沟槽内形成间隔物，并且在半导体衬底上的沟槽的底部的间隔物之间形成栅极电介质。 然后用栅极电极材料填充沟槽，该栅电极材料被化学机械地抛光以隔离沟槽内的栅极电极材料，并且去除第一层，留下栅极电介质，栅极电极和间隔物。
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2.发明授权Transistor with low resistance tip and method of fabrication in a CMOS process 失效具有低电阻尖端的晶体管和CMOS工艺中的制造方法
公开(公告)号：US06165826A
公开(公告)日：2000-12-26
申请号：US581243
申请日：1995-12-29
IPC分类号： H01L21/225 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/08 , H01L29/417 , H01L29/45 , H01L29/49 , H01L29/78
CPC分类号： H01L29/0847 , H01L21/2254 , H01L21/2257 , H01L21/2807 , H01L21/823814 , H01L21/823828 , H01L21/823864 , H01L29/41775 , H01L29/41783 , H01L29/45 , H01L29/4925 , H01L29/4933 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66613 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A novel transistor with a low resistance ultra shallow tip region and its method of fabrication in a complementary metal oxide semiconductor (CMOS) process. According to the preferred method of the present invention, a first gate dielectric and a first gate electrode are formed on a first portion of a semiconductor substrate having a first conductivity type, and a second gate dielectric and a said gate electrode are formed on a second portion of semiconductor substrate having a second conductivity type. A silicon nitride layer is formed over the first portion of the semiconductor substrate including the first gate electrode and over the second portion of the semiconductor substrate including the second gate electrode. The silicon nitride layer is removed from the second portion of the silicon substrate and from the top of the second gate electrode to thereby form a first pair of silicon nitride spacers adjacent to opposite sides of the second gate electrode. A pair of recesses are then formed in the second portion of the semiconductor substrate in alignment with the first pair of sidewall spacers. A selectively deposited semiconductor material is then formed in the recesses.
摘要翻译： 一种具有低电阻超浅尖端区域的新型晶体管及其在互补金属氧化物半导体（CMOS）工艺中制造的方法。 根据本发明的优选方法，在具有第一导电类型的半导体衬底的第一部分上形成第一栅极电介质和第一栅电极，并且在第二栅极电极上形成第二栅极电介质和所述栅电极 具有第二导电类型的半导体衬底的部分。 在包括第一栅电极的半导体衬底的第一部分之上以及包括第二栅电极的半导体衬底的第二部分之上形成氮化硅层。 从硅衬底的第二部分和第二栅电极的顶部去除氮化硅层，从而形成与第二栅电极的相对侧相邻的第一对氮化硅间隔物。 然后在半导体衬底的第二部分中与第一对侧壁间隔件对准地形成一对凹部。 然后在凹部中形成选择性淀积的半导体材料。
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公开(公告)号：US06326664B1
公开(公告)日：2001-12-04
申请号：US08971992
申请日：1997-11-17
申请人： Robert S. Chau , Chan-Hong Chern , Chia-Hong Jan , Kevin R. Weldon , Paul A. Packan , Leopoldo D. Yau
发明人： Robert S. Chau , Chan-Hong Chern , Chia-Hong Jan , Kevin R. Weldon , Paul A. Packan , Leopoldo D. Yau
IPC分类号： H01L2906
CPC分类号： H01L29/0847 , H01L21/2254 , H01L21/2257 , H01L21/2807 , H01L21/823814 , H01L21/823828 , H01L21/823864 , H01L29/41775 , H01L29/41783 , H01L29/45 , H01L29/4925 , H01L29/4933 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66613 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip comprising an ultra shallow region which extends beneath the gate electrode and a raised region.
摘要翻译： 具有低电阻超浅尖端区域的新型晶体管及其制造方法。 本发明的新型晶体管具有源极/漏极延伸部分或尖端，其包括在栅电极下方延伸的超浅区域和升高的区域。
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公开(公告)号：US5710450A
公开(公告)日：1998-01-20
申请号：US363749
申请日：1994-12-23
申请人： Robert S. Chau , Chan-Hong Chern , Chia-Hong Jan , Kevin R. Weldon , Paul A. Packan , Leopoldo D. Yau
发明人： Robert S. Chau , Chan-Hong Chern , Chia-Hong Jan , Kevin R. Weldon , Paul A. Packan , Leopoldo D. Yau
IPC分类号： H01L21/225 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/08 , H01L29/417 , H01L29/45 , H01L29/49 , H01L29/78 , H01L29/06 , H01L21/265
CPC分类号： H01L29/66613 , H01L21/2254 , H01L21/2257 , H01L21/2807 , H01L21/823814 , H01L21/823828 , H01L21/823864 , H01L29/0847 , H01L29/41775 , H01L29/41783 , H01L29/45 , H01L29/4925 , H01L29/4933 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip region comprising an ultra shallow region which extends beneath the gate electrode and a raised region.
摘要翻译： 具有低电阻超浅尖端区域的新型晶体管及其制造方法。 本发明的新型晶体管具有源/漏扩展或尖端区域，其包括在栅电极下方延伸的超浅区域和升高区域。
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5.发明授权Integrated dual layer emitter mask and emitter trench for BiCMOS processes 失效用于BiCMOS工艺的集成双层发射极掩模和发射极沟槽
公开(公告)号：US5856697A
公开(公告)日：1999-01-05
申请号：US895270
申请日：1997-07-14
IPC分类号： H01L21/331 , H01L21/8249 , H01L29/08 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/66272 , H01L21/8249 , H01L29/0804 , Y10S148/01 , Y10S148/011
摘要： A new method of isolating a polysilicon emitter from the base region of a bipolar transistor, trenching the polysilicon emitter into the semiconductor substrate, and maintaining a consistent base width of a bipolar transistor independent of variations in emitter mask thicknesses is disclosed. The polysilicon emitter isolation provides for better electrical breakdown characteristics between the emitter and the base by protecting the dielectric layer between the polysilicon emitter and base regions from defects and contamination associated with the BiCMOS manufacturing environment. The polysilicon emitter is trenched into the semiconductor substrate in order to reduce transistor operation problems associated with hot electron injection. Consistent base widths improve transistor performance uniformity thereby improving manufacturability and reliability.
摘要翻译： 公开了一种从双极晶体管的基极区域隔离多晶硅发射极的新方法，将多晶硅发射极沟槽到半导体衬底中，并保持独立于发射极掩模厚度变化的双极晶体管的一致的基底宽度。 多晶硅发射极隔离通过保护多晶硅发射极和基极区域之间的电介质层与BiCMOS制造环境相关的缺陷和污染来提供发射极和基极之间的更好的电击穿特性。 为了减少与热电子注入相关的晶体管操作问题，多晶硅发射极被沟入半导体衬底。 一致的基极宽度提高了晶体管的性能均匀性，从而提高了可制造性和可靠性。
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6.发明授权Method of making emitter trench BiCMOS using integrated dual layer emitter mask 失效使用集成双层发射器掩模制造发射极沟槽BiCMOS的方法
公开(公告)号：US5488003A
公开(公告)日：1996-01-30
申请号：US40673
申请日：1993-03-31
IPC分类号： H01L21/331 , H01L21/8249 , H01L29/08 , H01L21/265
CPC分类号： H01L29/66272 , H01L21/8249 , H01L29/0804 , Y10S148/01 , Y10S148/011
摘要： A new method of isolating a polysilicon emitter from the base region of a bipolar transistor, trenching the polysilicon emitter into the semiconductor substrate, and maintaining a consistent base width of a bipolar transistor independent of variations in emitter mask thicknesses is disclosed. The polysilicon emitter isolation provides for better electrical breakdown characteristics between the emitter and the base by protecting the dielectric layer between the polysilicon emitter and base regions from defects and contamination associated with the BiCMOS manufacturing environment. The polysilicon emitter is trenched into the semiconductor substrate in order to reduce transistor operation problems associated with hot electron injection. Consistent base widths improve transistor performance uniformity thereby improving manufacturability and reliability.
摘要翻译： 公开了一种从双极晶体管的基极区域隔离多晶硅发射极的新方法，将多晶硅发射极沟槽到半导体衬底中，并保持独立于发射极掩模厚度变化的双极晶体管的一致的基底宽度。 多晶硅发射极隔离通过保护多晶硅发射极和基极区域之间的电介质层与BiCMOS制造环境相关的缺陷和污染来提供发射极和基极之间的更好的电击穿特性。 为了减少与热电子注入相关的晶体管操作问题，多晶硅发射极被沟入半导体衬底。 一致的基极宽度提高了晶体管的性能均匀性，从而提高了可制造性和可靠性。
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7.发明授权
公开(公告)号：US5783478A
公开(公告)日：1998-07-21
申请号：US639776
申请日：1996-04-29
IPC分类号： H01L29/43 , H01L21/28 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/78 , H01L21/3205
CPC分类号： H01L29/6659 , H01L21/2807 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/665 , H01L29/78 , H01L2924/0002
摘要： A novel, reliable, high performance MOS transistor with a composite gate electrode which is compatible with standard CMOS fabrication processes. The composite gate electrode comprises a polysilicon layer formed on a highly conductive layer. The composite gate electrode is formed on a gate insulating layer which is formed on a silicon substrate. A pair of source/drain regions are formed in the substrate and are self-aligned to the outside edges of the composite gate electrode.
摘要翻译： 一种具有与标准CMOS制造工艺兼容的复合栅电极的新颖可靠的高性能MOS晶体管。 复合栅电极包括形成在高导电层上的多晶硅层。 复合栅电极形成在形成在硅衬底上的栅极绝缘层上。 在衬底中形成一对源极/漏极区，并且与复合栅电极的外边缘自对准。
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8.发明授权
公开(公告)号：US5625217A
公开(公告)日：1997-04-29
申请号：US384352
申请日：1995-02-02
IPC分类号： H01L29/43 , H01L21/28 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/6659 , H01L21/2807 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/665 , H01L29/78 , H01L2924/0002
摘要： A novel, reliable, high performance MOS transistor with a composite gate electrode which is compatible with standard CMOS fabrication processes. The composite gate electrode comprises a polysilicon layer formed on a highly conductive layer. The composite gate electrode is formed on a gate insulating layer which is formed on a silicon substrate. A pair of source/drain regions are formed in the substrate and are self-aligned to the outside edges of the composite gate electrode.
摘要翻译： 一种具有与标准CMOS制造工艺兼容的复合栅电极的新颖可靠的高性能MOS晶体管。 复合栅电极包括形成在高导电层上的多晶硅层。 复合栅电极形成在形成在硅衬底上的栅极绝缘层上。 在衬底中形成一对源极/漏极区，并且与复合栅电极的外边缘自对准。
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公开(公告)号：USRE38674E1
公开(公告)日：2004-12-21
申请号：US08528188
申请日：1995-09-14
IPC分类号： H01L2131
CPC分类号： H01L21/28185 , H01L21/02164 , H01L21/022 , H01L21/02211 , H01L21/02238 , H01L21/02255 , H01L21/02271 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/28238 , H01L21/31662 , H01L29/513 , H01L29/518 , Y10S148/118
摘要： A novel process for forming a robust, sub-100 Å oxide is disclosed. Native oxide growth is tightly controlled by flowing pure nitrogen during wafer push and nitrogen with a small amount of oxygen during temperature ramp and stabilization. First, a dry oxidation is performed in oxygen and 13% trichloroethane. Next, a wet oxidation in pyrogenic steam is performed to produce a total oxide thickness of approximately 80 Å. The oxide layer formed is ideally suited for use as a high integrity gate oxide below 100 Å. The invention is particularly useful in devices with advanced, recessed field isolation where sharp silicon edges are difficult to oxidize. For an oxide layer of more than 100 Å, a composite oxide stack is used which comprises 40-90 Å of pad oxide formed using the above novel process, and 60-200 Å of deposited oxide.
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10.发明授权
公开(公告)号：US5863832A
公开(公告)日：1999-01-26
申请号：US671968
申请日：1996-06-28
申请人： Brian Doyle , Quat T. Yu , Leopoldo D. Yau
发明人： Brian Doyle , Quat T. Yu , Leopoldo D. Yau
IPC分类号： H01L21/768 , H01L23/522 , H01L21/44 , H01L21/443
CPC分类号： H01L21/76834 , H01L21/7682 , H01L23/5222 , H01L21/76852 , H01L2924/0002 , Y10S148/012 , Y10S438/916 , Y10S438/977
摘要： The present invention provides an interconnect system. The interconnect system includes a substrate, a first dielectric layer deposited upon the substrate. The interconnect system further includes at least two electrically conductive interconnect lines formed upon the first dielectric layer. Each of the at least two interconnect lines have a top surface and side surfaces. Adjacent side surfaces of two adjacent interconnect lines define therebetween a space that has a dielectric constant substantially equal to 1. A dielectric film is bonded upon the top surface of the at least two interconnect lines. The dielectric film substantially prevents obstruction of the space by further process.
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