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    Transistor with low resistance tip and method of fabrication in a CMOS process
    2.
    发明授权
    Transistor with low resistance tip and method of fabrication in a CMOS process 失效
    具有低电阻尖端的晶体管和CMOS工艺中的制造方法

    公开(公告)号：US06165826A

    公开(公告)日：2000-12-26

    申请号：US581243

    申请日：1995-12-29

    申请人： Robert S. Chau ,  Chia-Hong Jan ,  Chan-Hong Chern ,  Leopoldo D. Yau

    发明人： Robert S. Chau ,  Chia-Hong Jan ,  Chan-Hong Chern ,  Leopoldo D. Yau

    IPC分类号： H01L21/225 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78

    CPC分类号： H01L29/0847 ,  H01L21/2254 ,  H01L21/2257 ,  H01L21/2807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66613 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

    摘要： A novel transistor with a low resistance ultra shallow tip region and its method of fabrication in a complementary metal oxide semiconductor (CMOS) process. According to the preferred method of the present invention, a first gate dielectric and a first gate electrode are formed on a first portion of a semiconductor substrate having a first conductivity type, and a second gate dielectric and a said gate electrode are formed on a second portion of semiconductor substrate having a second conductivity type. A silicon nitride layer is formed over the first portion of the semiconductor substrate including the first gate electrode and over the second portion of the semiconductor substrate including the second gate electrode. The silicon nitride layer is removed from the second portion of the silicon substrate and from the top of the second gate electrode to thereby form a first pair of silicon nitride spacers adjacent to opposite sides of the second gate electrode. A pair of recesses are then formed in the second portion of the semiconductor substrate in alignment with the first pair of sidewall spacers. A selectively deposited semiconductor material is then formed in the recesses.

    摘要翻译： 一种具有低电阻超浅尖端区域的新型晶体管及其在互补金属氧化物半导体（CMOS）工艺中制造的方法。 根据本发明的优选方法，在具有第一导电类型的半导体衬底的第一部分上形成第一栅极电介质和第一栅电极，并且在第二栅极电极上形成第二栅极电介质和所述栅电极 具有第二导电类型的半导体衬底的部分。 在包括第一栅电极的半导体衬底的第一部分之上以及包括第二栅电极的半导体衬底的第二部分之上形成氮化硅层。 从硅衬底的第二部分和第二栅电极的顶部去除氮化硅层，从而形成与第二栅电极的相对侧相邻的第一对氮化硅间隔物。 然后在半导体衬底的第二部分中与第一对侧壁间隔件对准地形成一对凹部。 然后在凹部中形成选择性淀积的半导体材料。

    Method of making emitter trench BiCMOS using integrated dual layer emitter mask
    5.
    发明授权
    Method of making emitter trench BiCMOS using integrated dual layer emitter mask 失效
    使用集成双层发射器掩模制造发射极沟槽BiCMOS的方法

    公开(公告)号：US5488003A

    公开(公告)日：1996-01-30

    申请号：US40673

    申请日：1993-03-31

    申请人： Stephen Chambers ,  Brian J. Brown ,  Chan-Hong Chern ,  Robert Chau ,  Leopoldo D. Yau

    发明人： Stephen Chambers ,  Brian J. Brown ,  Chan-Hong Chern ,  Robert Chau ,  Leopoldo D. Yau

    IPC分类号： H01L21/331 ,  H01L21/8249 ,  H01L29/08 ,  H01L21/265

    CPC分类号： H01L29/66272 ,  H01L21/8249 ,  H01L29/0804 ,  Y10S148/01 ,  Y10S148/011

    摘要： A new method of isolating a polysilicon emitter from the base region of a bipolar transistor, trenching the polysilicon emitter into the semiconductor substrate, and maintaining a consistent base width of a bipolar transistor independent of variations in emitter mask thicknesses is disclosed. The polysilicon emitter isolation provides for better electrical breakdown characteristics between the emitter and the base by protecting the dielectric layer between the polysilicon emitter and base regions from defects and contamination associated with the BiCMOS manufacturing environment. The polysilicon emitter is trenched into the semiconductor substrate in order to reduce transistor operation problems associated with hot electron injection. Consistent base widths improve transistor performance uniformity thereby improving manufacturability and reliability.

    摘要翻译： 公开了一种从双极晶体管的基极区域隔离多晶硅发射极的新方法，将多晶硅发射极沟槽到半导体衬底中，并保持独立于发射极掩模厚度变化的双极晶体管的一致的基底宽度。 多晶硅发射极隔离通过保护多晶硅发射极和基极区域之间的电介质层与BiCMOS制造环境相关的缺陷和污染来提供发射极和基极之间的更好的电击穿特性。 为了减少与热电子注入相关的晶体管操作问题，多晶硅发射极被沟入半导体衬底。 一致的基极宽度提高了晶体管的性能均匀性，从而提高了可制造性和可靠性。

    Integrated dual layer emitter mask and emitter trench for BiCMOS processes
    6.
    发明授权
    Integrated dual layer emitter mask and emitter trench for BiCMOS processes 失效
    用于BiCMOS工艺的集成双层发射极掩模和发射极沟槽

    公开(公告)号：US5856697A

    公开(公告)日：1999-01-05

    申请号：US895270

    申请日：1997-07-14

    申请人： Stephen Chambers ,  Brian J. Brown ,  Chan-Hong Chern ,  Robert Chau ,  Leopoldo D. Yau

    发明人： Stephen Chambers ,  Brian J. Brown ,  Chan-Hong Chern ,  Robert Chau ,  Leopoldo D. Yau

    IPC分类号： H01L21/331 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

    CPC分类号： H01L29/66272 ,  H01L21/8249 ,  H01L29/0804 ,  Y10S148/01 ,  Y10S148/011

    摘要： A new method of isolating a polysilicon emitter from the base region of a bipolar transistor, trenching the polysilicon emitter into the semiconductor substrate, and maintaining a consistent base width of a bipolar transistor independent of variations in emitter mask thicknesses is disclosed. The polysilicon emitter isolation provides for better electrical breakdown characteristics between the emitter and the base by protecting the dielectric layer between the polysilicon emitter and base regions from defects and contamination associated with the BiCMOS manufacturing environment. The polysilicon emitter is trenched into the semiconductor substrate in order to reduce transistor operation problems associated with hot electron injection. Consistent base widths improve transistor performance uniformity thereby improving manufacturability and reliability.

    摘要翻译： 公开了一种从双极晶体管的基极区域隔离多晶硅发射极的新方法，将多晶硅发射极沟槽到半导体衬底中，并保持独立于发射极掩模厚度变化的双极晶体管的一致的基底宽度。 多晶硅发射极隔离通过保护多晶硅发射极和基极区域之间的电介质层与BiCMOS制造环境相关的缺陷和污染来提供发射极和基极之间的更好的电击穿特性。 为了减少与热电子注入相关的晶体管操作问题，多晶硅发射极被沟入半导体衬底。 一致的基极宽度提高了晶体管的性能均匀性，从而提高了可制造性和可靠性。

    Integrated circuits with electrical fuses and methods of forming the same
    7.
    发明授权
    Integrated circuits with electrical fuses and methods of forming the same 有权
    具有电熔丝的集成电路及其形成方法

    公开(公告)号：US09524934B2

    公开(公告)日：2016-12-20

    申请号：US13302335

    申请日：2011-11-22

    申请人： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Kuoyuan (Peter) Hsu

    发明人： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Kuoyuan (Peter) Hsu

    IPC分类号： H01L21/8238 ,  H01L23/525 ,  H01L27/06 ,  H01L29/51 ,  H01L29/66

    CPC分类号： H01L23/5256 ,  H01L21/823437 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/11206 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming an integrated circuit includes forming at least one transistor over a substrate. Forming the at least one transistor includes forming a gate dielectric structure over a substrate. A work-function metallic layer is formed over the gate dielectric structure. A conductive layer is formed over the work-function metallic layer. A source/drain (S/D) region is formed adjacent to each sidewall of the gate dielectric structure. At least one electrical fuse is formed over the substrate. Forming the at least one electrical fuse includes forming a first semiconductor layer over the substrate. A first silicide layer is formed on the first semiconductor layer.

    摘要翻译： 形成集成电路的方法包括在衬底上形成至少一个晶体管。 形成至少一个晶体管包括在衬底上形成栅极电介质结构。 在栅介电结构上形成功函数金属层。 在功函数金属层上形成导电层。 源极/漏极（S / D）区域形成为与栅极电介质结构的每个侧壁相邻。 在衬底上形成至少一个电熔丝。 形成至少一个电熔丝包括在衬底上形成第一半导体层。 在第一半导体层上形成第一硅化物层。

    Multiple-phase clock generator
    8.
    发明授权
    Multiple-phase clock generator 有权
    多相时钟发生器

    公开(公告)号：US08884665B2

    公开(公告)日：2014-11-11

    申请号：US13084817

    申请日：2011-04-12

    申请人： Chih-Chang Lin ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Tao Wen Chung

    发明人： Chih-Chang Lin ,  Chan-Hong Chern ,  Ming-Chieh Huang ,  Tao Wen Chung

    IPC分类号： H03B19/00 ,  H03K5/15

    CPC分类号： H03K5/15013

    摘要： A multiple-phase clock generator includes at least one stage of dividers. A clock signal is supplied as a first stage clock input to dividers in a first stage of dividers. An N-th stage includes 2N dividers, where N is a positive integer number. Each divider in the first stage is configured to divide a first clock frequency of the first stage clock input by 2 to provide a first stage output. Each divider in the N-th stage is configured to divide an N-th clock frequency of an N-th stage clock input by 2 to provide an N-th stage output. The N-th stage outputs from the dividers in the N-th stage provide 2N-phase clock signals that are equally distributed with a same phase difference between adjacent phase clock signals.

    摘要翻译： 多相时钟发生器包括至少一个分频器级。 时钟信号作为第一级时钟输入提供给分频器的第一级中的分频器。 第N级包括2N个分频器，其中N是正整数。 第一级中的每个分频器被配置为将第一级时钟输入的第一时钟频率除以2以提供第一级输出。 第N级中的每个除法器被配置为将输入的第N级时钟的第N个时钟频率除以2以提供第N级输出。 在第N级的分频器的第N级输出提供2N相位时钟信号，它们在相邻的相位时钟信号之间以相同的相位差均匀分布。

    Decision feedback equalizer
    10.
    发明授权
    Decision feedback equalizer 有权
    决策反馈均衡器

    公开(公告)号：US08862951B2

    公开(公告)日：2014-10-14

    申请号：US13528877

    申请日：2012-06-21

    申请人： Ming-Chieh Huang ,  Chan-Hong Chern ,  Tao Wen Chung ,  Yuwen Swei ,  Chih-Chang Lin ,  Tsung-Ching Huang

    发明人： Ming-Chieh Huang ,  Chan-Hong Chern ,  Tao Wen Chung ,  Yuwen Swei ,  Chih-Chang Lin ,  Tsung-Ching Huang

    IPC分类号： G06F11/00 ,  H04L27/01

    CPC分类号： H04L25/03057 ,  H04L25/06 ,  H04L25/08

    摘要： A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.

    摘要翻译： 电路包括用于接收输入数据信号和包括先前数据位的反馈信号的求和电路。 求和电路被配置为将调节的输入数据信号输出到时钟和数据恢复电路。 第一触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第一比特组和具有小于输入数据信号的频率的频率的第一时钟信号 由第一求和电路接收。 第二触发器耦合到求和电路的输出，并且被配置为接收经调节的输入数据信号的第二组比特和具有小于输入数据信号的频率的频率的第二时钟信号 由第一求和电路接收。