公开(公告)号：US08570332B2

公开(公告)日：2013-10-29

申请号：US12569701

申请日：2009-09-29

Applicant: Chia-Lin Yang ,  Po-Han Wang ,  Yu-Jung Cheng

Inventor： Chia-Lin Yang ,  Po-Han Wang ,  Yu-Jung Cheng

IPC: G06F15/16 ,  G09G5/397

CPC classification number: G06T15/005 ,  G06F1/3203 ,  G06F1/3228 ,  G06F1/3243 ,  G06T2200/28 ,  Y02D10/152

Abstract: The invention relates to a power-gating control method for a graphics processing unit having a unified shader unit, which includes a plurality of shaders. The method includes the steps of: rendering a plurality of previous frames; calculating a first number of active shaders for rendering each previous frame, and a corresponding frame rate of each previous frame; determining a second number of active shaders for rendering a next frame immediately following the previous frame according to the first number of active shaders and the corresponding frame rate of each previous frame; and activating corresponding shaders through one or more power-gating control elements according to the second number of active shaders.

Abstract translation: 本发明涉及一种具有统一着色器单元的图形处理单元的功率门控控制方法，该单元包括多个着色器。 该方法包括以下步骤：渲染多个先前帧; 计算用于渲染每个先前帧的第一数目的活动着色器和每个先前帧的对应帧速率; 确定第二数目的活动着色器，用于根据所述第一数目的活动着色器和每个先前帧的相应帧速率紧接在所述先前帧之后渲染下一帧; 以及根据第二数量的活动着色器，通过一个或多个电源门控控制元件激活相应的着色器。

公开(公告)号：US20130175324A1

公开(公告)日：2013-07-11

申请号：US13348503

申请日：2012-01-11

Applicant: Hui-Shan Chang ,  Chia-Lin Hung ,  Chung Chieh Huang

Inventor： Hui-Shan Chang ,  Chia-Lin Hung ,  Chung Chieh Huang

IPC: B23K20/02 ,  B23K37/00

CPC classification number: H01L24/75 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/75303 ,  H01L2224/7531 ,  H01L2224/75312 ,  H01L2224/75745 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/9211 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/0401

Abstract: The present invention provides a method and a thermal compression head for flip chip bonding. The thermal compression head includes a main body and a contact portion. The main body has a main body opening. The contact portion has a contact surface and a plurality of openings. The openings communicate with the main body opening. When the contact surface of the contact portion is used to adsorb a chip, the contact surface of the chip has a plurality of adsorbed zones corresponding to the contact surface openings. After the chip is bonded to a substrate, the protrusions of the adsorbed zones are relatively slight. Therefore, the interconnection between the chip and the substrate is ensured.

Abstract translation: 本发明提供一种用于倒装芯片接合的方法和热压头。 热压头包括主体和接触部。 主体具有主体开口。 接触部分具有接触表面和多个开口。 开口与主体开口连通。 当接触部分的接触表面用于吸附芯片时，芯片的接触表面具有对应于接触表面开口的多个吸附区域。 在将芯片粘合到基板上之后，吸附区域的突出部分相对较小。 因此，确保了芯片和基板之间的互连。

公开(公告)号：US20130147057A1

公开(公告)日：2013-06-13

申请号：US13324405

申请日：2011-12-13

Applicant: Jaw-Juinn HORNG ,  Chia-Lin YU ,  Chung-Hui CHEN ,  Der-Chyang YEH ,  Yung-Chow PENG

Inventor： Jaw-Juinn HORNG ,  Chia-Lin YU ,  Chung-Hui CHEN ,  Der-Chyang YEH ,  Yung-Chow PENG

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to VDD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.

Abstract translation: 提供通过硅通孔（TSV）隔离结构，并且抑制诸如在由3D集成电路封装中使用的携带有源TSV的信号引起的时候可能传播通过半导体衬底的电噪声。 隔离TSV结构被氧化物衬垫和周围的掺杂剂杂质区包围。 周围的掺杂剂杂质区域可以是耦合到接地的P型掺杂剂杂质区域或者可以有利地连接到VDD的N型掺杂剂杂质区域。 TSV隔离结构有利地设置在有源信号承载TSV和有源半导体器件之间，并且TSV隔离结构可以形成为将有源信号传输TSV结构与有源半导体器件隔离的阵列。

公开(公告)号：US20130131535A1

公开(公告)日：2013-05-23

申请号：US13301459

申请日：2011-11-21

Applicant: Kuang-Tien Sun ,  Tzu-Wei Huang ,  Min-Chi Chen ,  Hsu Sun ,  Chia-Lin Sun

Inventor： Kuang-Tien Sun ,  Tzu-Wei Huang ,  Min-Chi Chen ,  Hsu Sun ,  Chia-Lin Sun

IPC: A61B5/0476

CPC classification number: A61B5/04842 ,  G06F3/015

Abstract: A brainwave control system and method operable through time differential event-related potential includes a brainwave capturing unit attached to a user's head, a brainwave signal processing apparatus and a display unit to display at least two sets of stimuli. The brainwave signal processing apparatus includes a signal processor connected to the brainwave capturing unit and a central processor. The signal processor converts brainwave signals generated by the user after having received a set of short time interval stimuli to digital signals. The central processor performs analysis and generates identification results and executes control commands accordingly. Thus user can rapidly and accurately execute his requirements of operation control so as to achieve non-contact operation control with improved usability and practicality.

Abstract translation: 通过时间差分事件相关电位可操作的脑波控制系统和方法包括附着在用户头部的脑波捕获单元，脑波信号处理装置和显示器，以显示至少两组刺激。 脑波信号处理装置包括连接到脑波捕获单元和中央处理器的信号处理器。 信号处理器在将数据信号接收到一组短时间间隔刺激之后，转换由用户产生的脑波信号。 中央处理器执行分析并产生识别结果并相应地执行控制命令。 因此用户可以快速，准确地执行其操作控制要求，从而实现非接触式操作控制，提高了可用性和实用性。

公开(公告)号：US08440511B1

公开(公告)日：2013-05-14

申请号：US13298264

申请日：2011-11-16

Applicant: Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Min-Ying Hsu ,  Hsin-Huei Wu ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

Inventor： Chin-I Liao ,  Chia-Lin Hsu ,  Ming-Yen Li ,  Min-Ying Hsu ,  Hsin-Huei Wu ,  Yung-Lun Hsieh ,  Chien-Hao Chen ,  Bo-Syuan Lee

IPC: H01L21/00

CPC classification number: H01L21/306 ,  H01L29/66795 ,  H01L29/7854

Abstract: A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer and a patterned hard mask sequentially formed thereon, removing the patterned hard mask, performing a thermal treatment to rounding the patterned semiconductor layer with a process temperature lower than 800° C., and sequentially forming a gate dielectric layer and a gate layer covering a portion of the patterned semiconductor layer on the semiconductor substrate.

Abstract translation: 一种用于制造多栅极晶体管器件的方法包括：提供具有图案化半导体层的半导体衬底和在其上依次形成的图案化硬掩模，去除图案化的硬掩模，进行热处理以使处理温度低于 800℃，并顺序地形成覆盖半导体衬底上的图案化半导体层的一部分的栅极电介质层和栅极层。

公开(公告)号：US08378993B2

公开(公告)日：2013-02-19

申请号：US12683439

申请日：2010-01-07

Applicant: Ling Li ,  Ying-Hui Chen ,  Chia-Lin Liu

Inventor： Ling Li ,  Ying-Hui Chen ,  Chia-Lin Liu

IPC: G06F3/045

CPC classification number: G06F3/044 ,  G02F1/13338 ,  G02F1/133514

Abstract: A capacitive touch display panel includes a first substrate, a second substrate, an opaque pattern, a plurality of transparent conductive sensor pads, and a plurality of non-transparent conductive patterns. The first substrate and the second substrate are disposed oppositely. The transparent conductive sensor pads are disposed on the second substrate. The non-transparent conductive patterns are disposed on the second substrate, and the non-transparent conductive patterns and the transparent conductive sensor pads are electrically connected and overlapping. The conductivity of the non-transparent conductive patterns is higher than that of the transparent conductive sensor pads, and the non-transparent conductive patterns are corresponding to the opaque pattern.

Abstract translation: 电容触摸显示面板包括第一基板，第二基板，不透明图案，多个透明导电传感器焊盘和多个不透明导电图案。 第一基板和第二基板相对设置。 透明导电传感器焊盘设置在第二基板上。 非透明导电图案设置在第二基板上，并且不透明导电图案和透明导电传感器垫片电连接和重叠。 不透明导电图案的导电率高于透明导电传感器焊盘的导电性，并且不透明导电图案对应于不透明图案。

公开(公告)号：US20130027004A1

公开(公告)日：2013-01-31

申请号：US13194908

申请日：2011-07-30

Applicant: Ting-Chin Tsen ,  Shu-Chia Lin ,  Wen-Yueh Hsieh

Inventor： Ting-Chin Tsen ,  Shu-Chia Lin ,  Wen-Yueh Hsieh

IPC: G05F1/10

CPC classification number: H02M5/293 ,  H02M1/32 ,  H02M2001/0022

Abstract: A power detection regulation device including a power detection signal generator, a power state detector and a regulated output unit is disclosed. The power detection signal generator receives the input power from an external power supply and generates a power detection signal. The power state detector generates a power state signal based on the power state derived from the power detection signal. The regulated output unit receives the power state signal and generates a driving signal to an external electrical device in accordance with the feedback signal from the external electrical device. The power state signal is provided for the external electrical element to perform relevant processes, and the regulated output device can output the predetermined driving signal on receiving the power state signal indicating some abnormal situation in the input power so as to maintain the normal operation performed by the actuating element in the external electrical device.

Abstract translation: 公开了一种功率检测调节装置，其包括功率检测信号发生器，功率状态检测器和调节输出单元。 功率检测信号发生器从外部电源接收输入电力并产生功率检测信号。 功率状态检测器基于从功率检测信号导出的功率状态产生功率状态信号。 调节输出单元接收功率状态信号，并根据来自外部电气设备的反馈信号向外部电气设备产生驱动信号。 为外部电气元件提供电源状态信号以执行相关处理，并且调节输出设备可以在接收到指示输入功率中的一些异常情况的电力状态信号时输出预定的驱动信号，以便保持正常操作 外部电气设备中的致动元件。

公开(公告)号：US20130011938A1

公开(公告)日：2013-01-10

申请号：US13176790

申请日：2011-07-06

Applicant: Wei-Che TSAO ,  Chia-Lin Hsu ,  Jen-Chieh Lin ,  Teng-Chun Tsai ,  Hsin-Kuo Hsu ,  Ya-Hsueh Hsieh ,  Ren-Peng Huang ,  Chih-Hsien Chen ,  Wen-Chin Lin ,  Yung-Lun Hsieh

Inventor： Wei-Che TSAO ,  Chia-Lin Hsu ,  Jen-Chieh Lin ,  Teng-Chun Tsai ,  Hsin-Kuo Hsu ,  Ya-Hsueh Hsieh ,  Ren-Peng Huang ,  Chih-Hsien Chen ,  Wen-Chin Lin ,  Yung-Lun Hsieh

IPC: H01L21/66 ,  H01L21/306 ,  H01L21/304

CPC classification number: H01L21/31053 ,  H01L21/3212 ,  H01L21/76898 ,  H01L22/12 ,  H01L22/26 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.

Abstract translation: 一种制造TSV的方法，其中该方法包括以下几个步骤：提供具有基板和ILD层（层间电介质层）的堆叠结构，其中穿透ILD层并进一步延伸到基板中的开口是 形成。 在堆叠结构和开口的侧壁上形成绝缘体层和金属阻挡层之后，在堆叠结构上形成顶部金属层以实现开口。 进行停止在阻挡层上的第一平面化处理以去除顶部金属层的一部分。 随后进行停止在ILD层上的第二平坦化处理以去除金属阻挡层的一部分，绝缘体层的一部分和顶部金属层的一部分，其中第二平坦化工艺具有由光线确定的抛光终点 干涉测量或电机电流。

公开(公告)号：US20120322265A1

公开(公告)日：2012-12-20

申请号：US13162776

申请日：2011-06-17

Applicant: Chun-Wei HSU ,  Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Chia-His Chen ,  Yen-Ming Chen

Inventor： Chun-Wei HSU ,  Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Chia-His Chen ,  Yen-Ming Chen

IPC: H01L21/304 ,  H01L21/306

CPC classification number: H01L21/31053 ,  H01L21/02065 ,  H01L29/517 ,  H01L29/66545

Abstract: A poly opening polish process includes the following steps. A semi-finished semiconductor component is provided. The semi-finished semiconductor component includes a substrate, a gate disposed on the substrate, and a dielectric layer disposed on the substrate and covering the gate. A first polishing process is applied onto the dielectric layer. A second polishing process is applied to the gate. The second polishing process utilizes a wetting solution including a water soluble polymer surfactant, an alkaline compound and water. The poly opening polish process can effectively remove an oxide residue formed in the chemical mechanical polish, thereby improving the performance of the integrated circuit and reducing the production cost of the integrated circuit.

Abstract translation: 多孔抛光工艺包括以下步骤。 提供半成品半导体元件。 半成品半导体部件包括基板，设置在基板上的栅极和设置在基板上并覆盖栅极的电介质层。 将第一抛光工艺施加到电介质层上。 第二次抛光工艺应用于浇口。 第二抛光工艺利用包含水溶性聚合物表面活性剂，碱性化合物和水的润湿溶液。 多孔抛光工艺可有效去除化学机械抛光中形成的氧化物残留物，从而提高集成电路的性能，降低集成电路的生产成本。

公开(公告)号：US20120304144A1

公开(公告)日：2012-11-29

申请号：US13568228

申请日：2012-08-07

Applicant: Chia-Lin Chuang

Inventor： Chia-Lin Chuang

IPC: G06F17/50

CPC classification number: H01L27/11898 ,  H01L23/5286 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention discloses a power mesh managing method utilized in an integrated circuit. The integrated circuit includes a standard cell and a standard-cell power supplying mesh corresponding to a first direction. The power mesh managing method includes: defining a power supplying network including a first plurality of power meshes growing along the first direction and a second plurality of power meshes growing along a second direction, and defining an assistant connecting network on a third metal layer, wherein the assistant connecting network includes a plurality of assistant connecting lines growing along the second direction, the first plurality of power meshes are formed on a first metal layer, the second plurality of power meshes on a second metal layer, the third metal layer is below the first metal layer, and the second metal layer is above the first metal layer.

Abstract translation: 本发明公开了一种集成电路中使用的电力网管理方法。 集成电路包括对应于第一方向的标准单元和标准单元供电网。 功率网管理方法包括：定义供电网络，其包括沿着第一方向生长的第一多个电力网格和沿着第二方向生长的第二多个电力网格，以及在第三金属层上限定辅助连接网络，其中 辅助连接网络包括沿着第二方向生长的多个辅助连接线，第一多个电网形成在第一金属层上，第二多个电源在第二金属层上，第三金属层在 第一金属层，第二金属层位于第一金属层的上方。