公开(公告)号：US20100320498A1

公开(公告)日：2010-12-23

申请号：US12788157

申请日：2010-05-26

Applicant: Chih-Sheng Lin ,  Che-Hsiung Wu

Inventor： Chih-Sheng Lin ,  Che-Hsiung Wu

IPC: H01L33/62

CPC classification number: H01L33/38

Abstract: A light-emitting diode device includes: a substrate; and a semiconductor layered structure including an n-type semiconductor layer that has an exposed region, and a p-type semiconductor layer that is disposed over the n-type semiconductor layer without extending over the exposed region. An electrode unit is electrically coupled to the semiconductor layered structure, and includes a first electrode and a second electrode. The second electrode has an electrode pad, an end node, and a connecting strip. The electrode pad is larger than the end node. The connecting strip is narrower than the end node.

Abstract translation: 发光二极管装置包括：基板; 以及包括具有曝光区域的n型半导体层的半导体层状结构以及设置在n型半导体层上方而不延伸在暴露区域上的p型半导体层。 电极单元电耦合到半导体层状结构，并且包括第一电极和第二电极。 第二电极具有电极焊盘，端部节点和连接条。 电极焊盘比端节点大。 连接条窄于端节点。

公开(公告)号：US20100237386A1

公开(公告)日：2010-09-23

申请号：US12564051

申请日：2009-09-22

Applicant: Chih-Sheng Lin ,  Chih-Wen Hsiao ,  Keng-Li Su

Inventor： Chih-Sheng Lin ,  Chih-Wen Hsiao ,  Keng-Li Su

IPC: H01L23/60 ,  H01L23/48

CPC classification number: H01L23/60 ,  H01L23/481 ,  H01L24/05 ,  H01L24/16 ,  H01L25/0657 ,  H01L27/0251 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/12036 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00

Abstract: An electrostatic discharge (ESD) structure for a 3-dimensional (3D) integrated circuit (IC) through-silicon via (TSV) device is provided. The ESD structure includes a substrate, a TSV device which is formed through the substrate and is equivalent to a resistance-inductance-capacitance (RLC) device, and at least one ESD device which is disposed in the substrate and electrically connected to one end of the TSV device. The ESD structure can protect the 3D IC TSV device.

Abstract translation: 提供了一种三维（3D）集成电路（IC）穿硅通孔（TSV）器件的静电放电（ESD）结构。 ESD结构包括衬底，通过衬底形成并等效于电阻 - 电感 - 电容（RLC）器件的TSV器件，以及至少一个ESD器件，其被布置在衬底中并电连接到 TSV设备。 ESD结构可以保护3D IC TSV器件。

公开(公告)号：US20100118617A1

公开(公告)日：2010-05-13

申请号：US12479612

申请日：2009-06-05

Applicant: Chih Sheng Lin ,  Min-Chuan Wang ,  Chih-Wen Hsiao ,  Keng-Li Su

Inventor： Chih Sheng Lin ,  Min-Chuan Wang ,  Chih-Wen Hsiao ,  Keng-Li Su

IPC: G11C7/10 ,  G11C5/14

CPC classification number: G11C8/08 ,  G11C7/12 ,  G11C11/1655 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/009

Abstract: A memory with improved write current is provided, including a bit line, a write switch and a control circuit. The write switch is coupled between a voltage source and the bit line, and has a control terminal. Based on a bit line select signal, the control circuit controls the electric conductance of the write switch and discharges/charges the parasitic capacitors of the write switch. The voltage source is turned on after the control terminal of the write switch reaches a pre-determined voltage level.

Abstract translation: 提供具有改善的写入电流的存储器，包括位线，写入开关和控制电路。 写开关耦合在电压源和位线之间，并且具有控制端子。 基于位线选择信号，控制电路控制写入开关的电导，并对写入开关的寄生电容器进行放电/充电。 在写开关的控制端达到预定电压电平之后，电压源接通。

公开(公告)号：US20070109841A1

公开(公告)日：2007-05-17

申请号：US11347052

申请日：2006-02-03

Applicant: Chih-Sheng Lin ,  Chia-Pao Chang ,  Jan-Ruei Lin

Inventor： Chih-Sheng Lin ,  Chia-Pao Chang ,  Jan-Ruei Lin

IPC: G11C11/00

CPC classification number: G11C7/067 ,  G11C7/062 ,  G11C7/14

Abstract: A memory device is provided. The device comprises a sense amplifier having a cell input terminal and a reference input terminal, a first sub-array coupled to the cell input terminal through a first switch and coupled to the reference input terminal through a second switch, a second sub-array coupled to the cell input terminal through a third switch and coupled to the reference input terminal through a fourth switch, and a reference cell array coupled between the second switch and the fourth switch and coupled to the reference input terminal.

Abstract translation: 提供存储器件。 该器件包括具有单元输入端和参考输入端的读出放大器，通过第一开关耦合到单元输入端并通过第二开关耦合到参考输入端的第一子阵列，第二子阵列耦合 通过第三开关耦合到单元输入端，并通过第四开关耦合到参考输入端，以及耦合在第二开关和第四开关之间并耦合到参考输入端的参考单元阵列。

公开(公告)号：US20130093454A1

公开(公告)日：2013-04-18

申请号：US13326331

申请日：2011-12-15

Applicant: Hsin-Chi Lai ,  Chih-Sheng Lin ,  Pi-Feng Chiu ,  Zhe-Hui Lin

Inventor： Hsin-Chi Lai ,  Chih-Sheng Lin ,  Pi-Feng Chiu ,  Zhe-Hui Lin

IPC: G01R31/26

CPC classification number: G01R31/318513 ,  G01R31/2812 ,  G01R31/31717 ,  H01L22/22

Abstract: A testing and repairing apparatus of through silicon via (TSV) disposed between a first and a second chips is provided. First terminals of a first and a second switches are coupled to a first terminal of the TSV. First terminals of a third and a fourth switches are coupled to a second terminal of the TSV. A first terminal of a first resister is coupled to a first voltage. A first selector is coupled between second terminals of the second switch and the first resister. A second selector is coupled between a second terminal of the fourth switch and a second voltage. A first control circuit detects the second terminal of the second switch, and controls the first switch, the second switch and the first selector. A second control circuit controls the third switch, the fourth switch and the second selector.

Abstract translation: 提供了设置在第一和第二芯片之间的通过硅通孔（TSV）的测试和修复设备。 第一和第二开关的第一端子耦合到TSV的第一端子。 第三和第四开关的第一端子耦合到TSV的第二端子。 第一电阻器的第一端子耦合到第一电压。 第一选择器耦合在第二开关的第二端子和第一电阻器之间。 第二选择器耦合在第四开关的第二端和第二电压之间。 第一控制电路检测第二开关的第二端子，并控制第一开关，第二开关和第一选择器。 第二控制电路控制第三开关，第四开关和第二选择器。

公开(公告)号：US20130059369A1

公开(公告)日：2013-03-07

申请号：US13351238

申请日：2012-01-17

Applicant: Chih-Sheng Lin ,  Sheng-Yi Chiu ,  Chien-Ya Kao

Inventor： Chih-Sheng Lin ,  Sheng-Yi Chiu ,  Chien-Ya Kao

IPC: C12M1/42

CPC classification number: C12M23/58 ,  C12M21/02 ,  C12M29/26 ,  C12M41/34 ,  C12M43/04

Abstract: A microalgae cultivation module for carbon reduction and biomass production is provided, which includes a first photobioreactor set, a second photobioreactor set, a gas switching device and a control unit. The gas switching device is communicated to the first and the second photobioreactor sets. The control unit is coupled to and controls the gas switching device, thereby aerating a waste gas into the first photobioreactor set and aerating air into the second photobioreactor set for a first predetermined time, then aerating the waste gas into the second photobioreactor set and aerating the air into the first photobioreactor set for a second predetermined time. The first and the second photobioreactor sets include a microalgae species.

Abstract translation: 提供了一种用于碳减少和生物质生产的微藻培养模块，其包括第一光生物反应器组，第二光生物反应器组，气体切换装置和控制单元。 气体切换装置与第一和第二光生物反应器组连通。 控制单元联接到并控制气体切换装置，从而将废气充气到第一光生物反应器组中，并将空气通入第二光生物反应器组中第一预定时间，然后将废气充气到第二光生物反应器组中， 进入第一光生物反应器的空气设定第二预定时间。 第一和第二光生物反应器组包括微藻种类。

公开(公告)号：US20120068177A1

公开(公告)日：2012-03-22

申请号：US13308523

申请日：2011-11-30

Applicant: Ra-Min Tain ,  Ming-Ji Dai ,  Shyh-Shyuan Sheu ,  Chih-Sheng Lin ,  Shih-Hsien Wu

Inventor： Ra-Min Tain ,  Ming-Ji Dai ,  Shyh-Shyuan Sheu ,  Chih-Sheng Lin ,  Shih-Hsien Wu

IPC: H01L25/07

CPC classification number: G01B7/18 ,  G01L1/18 ,  G01L1/2206 ,  H01L2224/16145

Abstract: A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface. The first heater comprises a plurality of first switches connected in series to generate heat.

Abstract translation: 提供了包括第一芯片，第一电路层，第一加热器，第一应力传感器和第二电路层的测量装置。 第一芯片具有第一通孔硅通孔，第一表面和与第一表面相对的第二表面。 第一电路层设置在第一表面上。 第一加热器和第一应力传感器设置在第一表面上并连接到第一电路层。 第二电路层设置在第二表面上。 第一加热器包括串联连接以产生热量的多个第一开关。

公开(公告)号：US20100178616A1

公开(公告)日：2010-07-15

申请号：US12651846

申请日：2010-01-04

Applicant: Chih-Sheng Lin ,  Che-Hsiung Wu

Inventor： Chih-Sheng Lin ,  Che-Hsiung Wu

IPC: G03F7/20

CPC classification number: H01L33/22 ,  C30B33/00

Abstract: A method of making a rough substrate includes: (a) forming a first oxide layer; (b) coating a photoresist layer; (c) exposing and developing the photoresist layer; (d) etching parts of the first oxide layer such that parts of the first oxide layer are formed into a plurality of sacrificial protrusions; (e) removing the photoresist regions; (f) depositing on the substrate layer and the sacrificial protrusions a second oxide layer; (g) etching the second oxide layer so as to leave portions of the second oxide layer; and (h) etching additionally the sacrificial protrusions, the substrate layer, and the portions of the second oxide layer, thereby producing a plurality of flat recess bottom faces, and substrate protrusions.

Abstract translation: 制作粗糙基板的方法包括：（a）形成第一氧化物层; （b）涂覆光致抗蚀剂层; （c）曝光和显影光刻胶层; （d）蚀刻第一氧化物层的部分，使得第一氧化物层的部分形成多个牺牲突起; （e）去除光致抗蚀剂区域; （f）在所述基底层和所述牺牲突起上沉积第二氧化物层; （g）蚀刻第二氧化物层以留下第二氧化物层的部分; 以及（h）另外蚀刻所述牺牲突起，所述基底层和所述第二氧化物层的所述部分，由此产生多个平坦凹陷底面和基底突起。

公开(公告)号：US07738289B2

公开(公告)日：2010-06-15

申请号：US12155787

申请日：2008-06-10

Applicant: Min Chuan Wang ,  Chih Sheng Lin ,  Keng Li Su ,  Wei Chun Chang

Inventor： Min Chuan Wang ,  Chih Sheng Lin ,  Keng Li Su ,  Wei Chun Chang

IPC: G11C11/00

CPC classification number: G11C11/5607 ,  G11C11/16 ,  G11C29/08 ,  G11C2211/5634

Abstract: The present invention relates to a memory accessing circuit, which is for accessing a memory circuit with 2N impedance states. The memory accessing circuit includes a testing signal generating circuit, for generating a testing signal by detecting the impedance state of the memory circuit; a reference signal generating circuit, for generating 2N−1 reference signals by detecting the impedance states of a reference circuit having 2N−1 impedance paths; a median signal generating circuit, for generating (2N−1)−1, median signals by receiving the 2N−1 reference signals; and a comparing circuit, for comparing the testing signal and the (2N−1) median signals. The present invention further provides a memory accessing method thereof.

Abstract translation: 本发明涉及一种用于访问具有2N个阻抗状态的存储器电路的存储器存取电路。 存储器访问电路包括测试信号发生电路，用于通过检测存储器电路的阻抗状态来产生测试信号; 参考信号发生电路，用于通过检测具有2N-1个阻抗路径的参考电路的阻抗状态来产生2N-1个参考信号; 中间信号发生电路，用于通过接收2N-1个参考信号来产生（2N-1）-1个中间信号; 以及用于比较测试信号和（2N-1）个中值信号的比较电路。 本发明还提供一种其存储器访问方法。

公开(公告)号：US20090303042A1

公开(公告)日：2009-12-10

申请号：US12262152

申请日：2008-10-30

Applicant: Kai-Tai Song ,  Chia-Hao Lin ,  Chih-Sheng Lin ,  Su-Hen Yang

Inventor： Kai-Tai Song ,  Chia-Hao Lin ,  Chih-Sheng Lin ,  Su-Hen Yang

IPC: G08B13/00

CPC classification number: G08B25/009 ,  G08B13/19645 ,  G08B13/19647

Abstract: This invention is an intruder detection system which integrates wireless sensor network and security robots. Multiple ZigBee wireless sensor modules installed in the environment can detect intruders and abnormal conditions with various sensors, and transmit alert to the monitoring center and security robot via the wireless mesh network. The robot can navigate in the environment autonomously and approach to a target place using its localization system. If any possible intruder is detected, the robot can approach to that location, and transmit images to the mobile devices of the securities and users, in order to determine the exact situation in real time.

Abstract translation: 本发明是一种综合无线传感器网络和安全机器人的入侵者检测系统。 安装在环境中的多个ZigBee无线传感器模块可以通过各种传感器检测入侵者和异常情况，并通过无线网状网络向监控中心和安全机器人发送警报。 机器人可以自主地在环境中导航，并使用其定位系统接近目标地点。 如果检测到任何可能的入侵者，机器人可以接近该位置，并将图像发送到证券和用户的移动设备，以便实时确定确切的情况。