公开(公告)号：US20100210189A1

公开(公告)日：2010-08-19

申请号：US12370662

申请日：2009-02-13

Applicant: Kun-Ku Hung ,  Zin-Chang Wei ,  Huang Soon Kang ,  Chyi-Shyuan Chern

Inventor： Kun-Ku Hung ,  Zin-Chang Wei ,  Huang Soon Kang ,  Chyi-Shyuan Chern

IPC: B24B57/02 ,  B24B7/20 ,  B24B29/00

CPC classification number: B24B57/02 ,  B24B37/04

Abstract: A chemical mechanical polishing method and apparatus provides a deformable, telescoping slurry dispenser arm coupled to a dispenser head that may be arcuate in shape and may also be a bendable telescoping member that can be adjusted to vary the number of slurry dispenser ports and the degree of curvature of the dispenser head. The dispenser arm may additionally include slurry dispenser ports therein. The dispenser arm may advantageously be formed of a plurality of nested tubes that are slidable with respect to one another. The adjustable dispenser arm may pivot about a pivot point and can be variously positioned to accommodate different sized polishing pads used to polish substrates of different dimensions and the bendable, telescoping slurry dispenser arm and dispenser head provide uniform slurry distribution to any of various wafer polishing locations, effective slurry usage and uniform polishing profiles in each case.

Abstract translation: 化学机械抛光方法和装置提供了可变形的，可伸缩的浆料分配器臂，其联接到分配器头部，其可以是弓形的形状，并且还可以是可弯曲的伸缩构件，其可以被调节以改变浆料分配器端口的数量和 分配头的曲率。 分配器臂可以另外包括其中的浆料分配器端口。 分配器臂可以有利地由可相对于彼此滑动的多个嵌套管形成。 可调节的分配器臂可围绕枢转点枢转并且可以被不同地定位以适应用于抛光不同尺寸的基板的不同尺寸的抛光垫，并且可弯曲的可伸缩浆料分配器臂和分配器头部向各种晶片抛光位置 ，有效的浆料使用和均匀的抛光轮廓在每种情况下。

公开(公告)号：US20100163078A1

公开(公告)日：2010-07-01

申请号：US12347433

申请日：2008-12-31

Applicant: Tzu-Jeng Hsu ,  Chi-Ming Yang ,  Chyi Shyuan Chern

Inventor： Tzu-Jeng Hsu ,  Chi-Ming Yang ,  Chyi Shyuan Chern

IPC: B08B7/04 ,  B08B3/02

CPC classification number: B08B3/022 ,  H01L21/67051

Abstract: A method includes spinning a semiconductor wafer about an axis normal to a major surface of the wafer. The wafer is translated in a direction parallel to the major surface with an oscillatory motion, while spinning the wafer. A material is sprayed from first and second nozzles or orifices at respective first and second locations on the major surface of the wafer simultaneously while spinning the wafer and translating the wafer.

Abstract translation: 一种方法包括围绕与晶片的主表面垂直的轴旋转半导体晶片。 在旋转晶片的同时，使晶片在与主表面平行的方向上以振荡的方式平移。 在旋转晶片并平移晶片的同时，在晶片的主表面上的相应的第一和第二位置处的第一和第二喷嘴或孔口喷射材料。

公开(公告)号：US20100140716A1

公开(公告)日：2010-06-10

申请号：US12332057

申请日：2008-12-10

Applicant: Simon Su-Horng Lin ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

Inventor： Simon Su-Horng Lin ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823857 ,  H01L21/28079 ,  H01L21/823842 ,  H01L27/0922 ,  H01L29/4958

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having a first region and a second region; a first gate stack of an n-type field-effect transistor (FET) in the first region; and a second gate stack of a p-type FET in the second region. The first gate stack includes a high k dielectric layer on the semiconductor substrate, a first crystalline metal layer in a first orientation on the high k dielectric layer, and a conductive material layer on the first crystalline metal layer. The second gate stack includes the high k dielectric layer on the semiconductor substrate, a second crystalline metal layer in a second orientation on the high k dielectric layer, and the conductive material layer on the second crystalline metal layer.

Abstract translation: 本发明提供集成电路。 集成电路包括具有第一区域和第二区域的半导体衬底; 在所述第一区域中的n型场效应晶体管（FET）的第一栅极堆叠; 以及第二区域中的p型FET的第二栅极堆叠。 第一栅极堆叠包括在半导体衬底上的高k电介质层，在高k电介质层上具有第一取向的第一晶体金属层和第一晶体金属层上的导电材料层。 第二栅极堆叠包括半导体衬底上的高k电介质层，在高k电介质层上具有第二取向的第二晶体金属层和第二晶体金属层上的导电材料层。

公开(公告)号：US20070082581A1

公开(公告)日：2007-04-12

申请号：US11245532

申请日：2005-10-07

Applicant: Volume Chien ,  Chyi-Shyuan Chern ,  Yu Yuan Kuo ,  Ming-Te Mo

Inventor： Volume Chien ,  Chyi-Shyuan Chern ,  Yu Yuan Kuo ,  Ming-Te Mo

IPC: B24B49/00 ,  G06F19/00

CPC classification number: B24B37/04 ,  B24B51/00

Abstract: A system of process control is provided. The system comprises a first processing tool, a first sensor, a second processing tool, and a processor. The first processing tool processes a first workpiece. The first sensor provides real-time monitoring (RTM) data of the first processing tool while processing the first workpiece. The second processing tool processes the first workpiece subsequent to the first processing tool. The processor adjusts, according to the real-time monitoring data and a preset program, the first processing tool for processing a second workpiece, and the second processing tool for processing the first workpiece.

Abstract translation: 提供了一种过程控制系统。 该系统包括第一处理工具，第一传感器，第二处理工具和处理器。 第一加工工具处理第一工件。 第一个传感器在处理第一个工件时提供第一个处理工具的实时监控（RTM）数据。 第二处理工具在第一处理工具之后处理第一工件。 处理器根据实时监视数据和预设程序调整用于处理第二工件的第一处理工具和用于处理第一工件的第二处理工具。

公开(公告)号：US09324624B2

公开(公告)日：2016-04-26

申请号：US13431165

申请日：2012-03-27

Applicant: Chyi-Shyuan Chern ,  Hsin-Hsien Wu ,  Yung-Hsin Yang ,  Ching-Hua Chiu

Inventor： Chyi-Shyuan Chern ,  Hsin-Hsien Wu ,  Yung-Hsin Yang ,  Ching-Hua Chiu

IPC: G01R31/26 ,  H01L21/66 ,  H01L33/00 ,  H01L33/22

CPC classification number: H01L22/12 ,  H01L22/20 ,  H01L33/0095 ,  H01L33/22

Abstract: The present disclosure involves a method of fabricating a light-emitting diode (LED) wafer. The method first determines a target surface morphology for the LED wafer. The target surface morphology yields a maximum light output for LEDs on the LED wafer. The LED wafer is etched to form a roughened wafer surface. Thereafter, using a laser scanning microscope, the method investigates an actual surface morphology of the LED wafer. Afterwards, if the actual surface morphology differs from the target surface morphology beyond an acceptable limit, the method repeats the etching step one or more times. The etching is repeated by adjusting one or more etching parameters.

Abstract translation: 本发明涉及一种制造发光二极管（LED）晶片的方法。 该方法首先确定LED晶片的目标表面形态。 目标表面形态为LED晶圆上的LED产生最大的光输出。 蚀刻LED晶片以形成粗糙的晶片表面。 此后，使用激光扫描显微镜，该方法研究了LED晶片的实际表面形态。 此后，如果实际的表面形态与目标表面形态不同，超过可接受的极限，则该方法重复一次或多次蚀刻步骤。 通过调整一个或多个蚀刻参数重复蚀刻。

公开(公告)号：US09048186B2

公开(公告)日：2015-06-02

申请号：US12879371

申请日：2010-09-10

Applicant: Kuo Bin Huang ,  Hsin-Chien Lu ,  Ryan Chia-Jen Chen ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

Inventor： Kuo Bin Huang ,  Hsin-Chien Lu ,  Ryan Chia-Jen Chen ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Chin-Hsiang Lin

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/02 ,  H01L21/8238

CPC classification number: H01L21/28238 ,  H01L21/02071 ,  H01L21/823842 ,  H01L21/823857

Abstract: A method for forming an integrated circuit is provided. The method includes forming a gate dielectric structure over a substrate. A titanium-containing sacrificial layer is formed, contacting the gate dielectric structure. The whole titanium-containing sacrificial layer is substantially removed.

Abstract translation: 提供一种用于形成集成电路的方法。 该方法包括在衬底上形成栅极电介质结构。 形成与该栅电介质结构接触的含钛牺牲层。 基本上除去了整个含钛牺牲层。

公开(公告)号：US08623141B2

公开(公告)日：2014-01-07

申请号：US12467375

申请日：2009-05-18

Applicant: Yi-Pin Chang ,  Chyi Shyuan Chern

Inventor： Yi-Pin Chang ,  Chyi Shyuan Chern

IPC: C23C16/00 ,  G05D16/20 ,  F15C3/00 ,  C23F1/00

CPC classification number: F16K51/02 ,  Y10T137/0379 ,  Y10T137/86002 ,  Y10T137/86027 ,  Y10T137/86083 ,  Y10T137/87684

Abstract: A vacuum system for semiconductor fabrication. The system includes a vacuum chamber for performing a semiconductor fabrication process, a vacuum source, and a piping system fluidly connecting the vacuum chamber to the vacuum source. In one embodiment, the piping system is configured without a horizontal flow path section of piping. In some embodiments, the piping system includes a first piping branch and a second piping branch. The first and second piping branches preferably have a symmetrical configuration with respect to the vacuum source. In yet other embodiments, the first and second piping branches preferably each include a throttle valve.

Abstract translation: 一种用于半导体制造的真空系统。 该系统包括用于执行半导体制造工艺的真空室，真空源和将真空室流体连接到真空源的管道系统。 在一个实施例中，管道系统被配置为没有管道的水平流动路径部分。 在一些实施例中，管道系统包括第一管道分支和第二管道分支。 第一和第二管道分支优选地具有相对于真空源的对称构造。 在其他实施例中，第一和第二管道分支优选地各自包括节流阀。

公开(公告)号：US08598617B2

公开(公告)日：2013-12-03

申请号：US13557272

申请日：2012-07-25

Applicant: Chih-Kuang Yu ,  Chyi Shyuan Chern ,  Hsing-Kuo Hsia ,  Hung-Yi Kuo

Inventor： Chih-Kuang Yu ,  Chyi Shyuan Chern ,  Hsing-Kuo Hsia ,  Hung-Yi Kuo

IPC: H01L33/00

CPC classification number: H01L25/0753 ,  H01L24/24 ,  H01L24/82 ,  H01L33/0079 ,  H01L33/44 ,  H01L33/62 ,  H01L2224/73267 ,  H01L2924/01029 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2933/0033 ,  H01L2924/00

Abstract: An LED array comprises a growth substrate and at least two separated LED dies grown over the growth substrate. Each of LED dies sequentially comprise a first conductive type doped layer, a multiple quantum well layer and a second conductive type doped layer. The LED array is bonded to a carrier substrate. Each of separated LED dies on the LED array is simultaneously bonded to the carrier substrate. The second conductive type doped layer of each of separated LED dies is proximate to the carrier substrate. The first conductive type doped layer of each of LED dies is exposed. A patterned isolation layer is formed over each of LED dies and the carrier substrate. Conductive interconnects are formed over the patterned isolation layer to electrically connect the at least separated LED dies and each of LED dies to the carrier substrate.

Abstract translation: LED阵列包括生长衬底和在生长衬底上生长的至少两个分离的LED管芯。 每个LED管芯依次包括第一导电型掺杂层，多量子阱层和第二导电型掺杂层。 LED阵列结合到载体衬底。 LED阵列上的每个分离的LED管芯同时结合到载体衬底。 每个分离的LED管芯的第二导电型掺杂层靠近载体衬底。 每个LED管芯的第一导电型掺杂层被暴露。 在每个LED管芯和载体衬底上形成图案化隔离层。 导电互连形成在图案化的隔离层上，以将至少分离的LED管芯和每个LED管芯电连接到载体衬底。

公开(公告)号：US20120286240A1

公开(公告)日：2012-11-15

申请号：US13557272

申请日：2012-07-25

Applicant: Chih-Kuang Yu ,  Chyi Shyuan Chern ,  Hsing-Kuo Hsia ,  Hung-Yi Kuo

Inventor： Chih-Kuang Yu ,  Chyi Shyuan Chern ,  Hsing-Kuo Hsia ,  Hung-Yi Kuo

IPC: H01L33/06

CPC classification number: H01L25/0753 ,  H01L24/24 ,  H01L24/82 ,  H01L33/0079 ,  H01L33/44 ,  H01L33/62 ,  H01L2224/73267 ,  H01L2924/01029 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2933/0033 ,  H01L2924/00

Abstract: An LED array comprises a growth substrate and at least two separated LED dies grown over the growth substrate. Each of LED dies sequentially comprise a first conductive type doped layer, a multiple quantum well layer and a second conductive type doped layer. The LED array is bonded to a carrier substrate. Each of separated LED dies on the LED array is simultaneously bonded to the carrier substrate. The second conductive type doped layer of each of separated LED dies is proximate to the carrier substrate. The first conductive type doped layer of each of LED dies is exposed. A patterned isolation layer is formed over each of LED dies and the carrier substrate. Conductive interconnects are formed over the patterned isolation layer to electrically connect the at least separated LED dies and each of LED dies to the carrier substrate.

Abstract translation: LED阵列包括生长衬底和在生长衬底上生长的至少两个分离的LED管芯。 每个LED管芯依次包括第一导电型掺杂层，多量子阱层和第二导电型掺杂层。 LED阵列结合到载体衬底。 LED阵列上的每个分离的LED管芯同时结合到载体衬底。 每个分离的LED管芯的第二导电型掺杂层靠近载体衬底。 每个LED管芯的第一导电型掺杂层被暴露。 在每个LED管芯和载体衬底上形成图案化隔离层。 导电互连形成在图案化的隔离层上，以将至少分离的LED管芯和每个LED管芯电连接到载体衬底。

公开(公告)号：US20120256187A1

公开(公告)日：2012-10-11

申请号：US13082238

申请日：2011-04-07

Applicant: Chih-Kuang Yu ,  Chyi Shyuan Chern

Inventor： Chih-Kuang Yu ,  Chyi Shyuan Chern

IPC: H01L33/02 ,  H01L33/62 ,  H01L33/22

CPC classification number: H01L25/0753 ,  H01L27/153 ,  H01L33/0079 ,  H01L33/32 ,  H01L33/46 ,  H01L33/486 ,  H01L33/50 ,  H01L33/507 ,  H01L33/62 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides one embodiment of a light-emitting structure. The light-emitting structure includes a carrier substrate having first metal features; a transparent substrate having second metal features; a plurality of light-emitting diodes (LEDs) bonded with the carrier substrate and the transparent substrate, sandwiched between the carrier substrate and the transparent substrate; and metal pillars bonded to the carrier substrate and the transparent substrate, each of the metal pillars being disposed between adjacent two of the plurality of LEDs, wherein the first metal features, the second metal features and the metal pillars are configured to electrically connect the plurality of LEDs.

Abstract translation: 本公开提供了发光结构的一个实施例。 发光结构包括具有第一金属特征的载体衬底; 具有第二金属特征的透明基板; 与载体基板和透明基板结合的多个发光二极管（LED）夹在载体基板和透明基板之间; 以及结合到所述载体基板和所述透明基板的金属柱，每个所述金属柱设置在所述多个LED的相邻两个之间，其中所述第一金属特征，所述第二金属特征和所述金属柱被配置为电连接所述多个 的LED。