公开(公告)号：US20210351121A1

公开(公告)日：2021-11-11

申请号：US17085433

申请日：2020-10-30

Applicant: Cree, Inc.

Inventor： Mitch Flowers ,  Erwin Cohen ,  Alexander Komposch ,  Larry Christopher Wall

IPC: H01L23/528

Abstract: A package includes a circuit that includes at least one active area and at least one secondary device area, a support configured to support the circuit, and a die attach material. The circuit being mounted on the support using the die attach material and the die attach material including at least one channel configured to allow gases generated during curing of the die attach material to be released from the die attach material.

公开(公告)号：US20210343679A1

公开(公告)日：2021-11-04

申请号：US16863188

申请日：2020-04-30

Applicant: Cree, Inc.

Inventor： Kenneth P. Brewer ,  Warren Brakensiek

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/64

Abstract: Fabrication of a bondwire inductor between connection pads of a semiconductor package using a wire bonding process is disclosed herein. To that end, the bondwire inductor is fabricated by extending a bondwire connecting two connection pads of the semiconductor package around a dielectric structure, e.g., a dielectric post or posts, disposed between the connection pads a defined amount. In so doing, the bondwire inductor adds inductance between the connection pads, where the added inductance is defined by factors which at least include the amount the bondwire extends around the dielectric structure. Such additional inductance may be particularly beneficial for certain semiconductor devices and/or circuits, e.g., monolithic microwave integrated circuits (MMICs) to control or supplement impedance matching, harmonic termination, matching biasing, etc.

公开(公告)号：US20210336021A1

公开(公告)日：2021-10-28

申请号：US16854959

申请日：2020-04-22

Applicant: Cree, Inc.

Inventor： Daniel Jenner Lichtenwalner ,  Brett Hull ,  Edward Robert Van Brunt ,  Shadi Sabri ,  Matt N. McCain

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/739 ,  H01L29/66 ,  H01L29/40 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor layer structure that includes silicon carbide, a gate dielectric layer on the semiconductor layer structure, and a gate electrode on the gate dielectric layer opposite the semiconductor layer structure. In some embodiments, a periphery of a portion of the gate dielectric layer that underlies the gate electrode is thicker than a central portion of the gate dielectric layer, and a lower surface of the gate electrode has recessed outer edges such as rounded and/or beveled outer edges.

公开(公告)号：US11139810B2

公开(公告)日：2021-10-05

申请号：US16524726

申请日：2019-07-29

Applicant: Cree, Inc.

Inventor： Cam Pham ,  Alejandro Esquivel Rodriguez

IPC: H03K17/082

Abstract: Support circuitry for a power transistor includes a feedback switching element and switching control circuitry. The feedback switching element is coupled between a Kelvin connection node and a second power switching node. The switching control circuitry is configured to cause the feedback switching element to couple the Kelvin connection node to the second power switching node after the power transistor is switched from a blocking mode of operation to a conduction mode of operation and cause the feedback switching element to isolate the Kelvin connection node from the second power switching node before the power transistor is switched from the conduction mode of operation to the blocking mode of operation.

公开(公告)号：US20210272298A1

公开(公告)日：2021-09-02

申请号：US16804776

申请日：2020-02-28

Applicant: Cree, Inc.

Inventor： Robert Tyler Leonard ,  Matthew David Conrad ,  Edward Robert Van Brunt

IPC: G06T7/33 ,  G06T3/00

Abstract: Wafer images and related alignment methods for crystalline wafers are disclosed. Certain aspects relate to accessing and aligning images of a same or similar crystalline wafer captured from different imaging sources. Alignment may include determining spatial differences between shared crystalline features in various wafer images of the same or similar crystalline wafer and transforming at least one of the images according to the determined spatial differences. With sufficient alignment, information may be associated and/or transferred between the various images, thereby providing the capability of forming a combined wafer image and sub-images thereof with high resolution and spatial coordination between different image sources. Certain aspects relate to development of nondestructive, high fidelity defect characterization and/or dislocation counting methods in crystalline materials based on modern deep convolutional neural networks (DCNN).

公开(公告)号：US20210265249A1

公开(公告)日：2021-08-26

申请号：US16797290

申请日：2020-02-21

Applicant: Cree, Inc.

Inventor： Alexander Komposch ,  Simon Ward ,  Madhu Chidurala

IPC: H01L23/498 ,  H01L23/66

Abstract: A device includes: a surface mount device carrier configured to be mounted to a metal submount of a transistor package, said surface mount device carrier includes an insulating substrate includes a top surface and a bottom surface and a first pad and a second pad arranged on a top surface of said surface mount device carrier; at least one surface mount device includes a first terminal and a second terminal, said first terminal of said surface mount device mounted to said first pad and said second terminal mounted to said second pad; and at least one of the first terminal and the second terminal being configured to be isolated from the metal submount by said insulating substrate, where at least one of the first pad and the second pad are configured as wire bond pads.

公开(公告)号：US11094848B2

公开(公告)日：2021-08-17

申请号：US16542458

申请日：2019-08-16

Applicant: Cree, Inc.

Inventor： Luis Breva ,  Colin Stuart ,  Michael Check

IPC: H01L33/38 ,  H01L33/40 ,  H01L33/46 ,  H01L33/62 ,  H01L33/22 ,  H01L33/32

Abstract: Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chip structures are disclosed. LED chip structures are disclosed that include reduced bonding topography between active LED structures and carrier submounts. For certain LED chip structures, active LED structures are formed on a growth substrate and subsequently bonded to a carrier substrate. Bonding between active LED structures and carrier submounts is typically provided by metal bonding materials. By providing reduced bonding topography between active LED structures and carrier submounts, bonding strength of metal bonding materials may be improved. Electrical connection configurations for certain layers of active LED structures are disclosed that promote reduced bonding topography. Peripheral border configurations of carrier submounts are also disclosed with that promote reduced bonding topography along the peripheral borders.

公开(公告)号：US20210249572A1

公开(公告)日：2021-08-12

申请号：US16664686

申请日：2019-10-25

Applicant: CREE, INC.

Inventor： Arthur Pun ,  Jeremy Nevins ,  Jesse Reiherzer ,  Joseph Clark

IPC: H01L33/54 ,  H01L25/075

Abstract: LED packages are disclosed that are compact and efficiently emit light, and can comprise encapsulants with planar surfaces that refract and/or reflect light within the package encapsulant. The LED package are also directed to features or arrangements that allow for improved or tailored emission characteristic for LED packages according to the present invention. Some of these features or arrangements include, but are not limited to, higher ratio of light source size to submount size, the used of particular materials (e.g. different silicones) for the LED package layers, improved arrangement of a reflective layer, improved composition and arrangement of the phosphor layer, tailoring the shape of the encapsulant, and/or improving the bonds between the layers. There are only some of the improvements disclosed herein, with some of these resulting in LED packages the emit light with a higher luminous intensity over conventional LED packages.

公开(公告)号：US20210233877A1

公开(公告)日：2021-07-29

申请号：US17228978

申请日：2021-04-13

Applicant: CREE, INC.

Inventor： Xikun ZHANG ,  Dejiang CHANG ,  Bill AGAR ,  Michael LEFEVRE ,  Alexander KOMPOSCH

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/495 ,  H01L23/498 ,  H01L25/07 ,  H01L25/00 ,  H01L29/16

Abstract: A multi-die package includes a thermally conductive flange, a first semiconductor die made of a first semiconductor material attached to the thermally conductive flange via a first die attach material, a second semiconductor die attached to the same thermally conductive flange as the first semiconductor die via a second die attach material, and leads attached to the thermally conductive flange or to an insulating member secured to the flange. The leads are configured to provide external electrical access to the first and second semiconductor dies. The second semiconductor die is made of a second semiconductor material different than the first semiconductor material. Additional multi-die package embodiments are described.

公开(公告)号：US20210230769A1

公开(公告)日：2021-07-29

申请号：US16775407

申请日：2020-01-29

Applicant: Cree, Inc.

Inventor： Yuri Khlebnikov ,  Robert T. Leonard ,  Elif Balkas ,  Steven Griffiths ,  Valeri Tsvetkov ,  Michael Paisley

IPC: C30B29/36 ,  H01L29/32 ,  H01L29/16 ,  C30B23/02

Abstract: Silicon carbide (SiC) wafers, SiC boules, and related methods are disclosed that provide improved dislocation distributions. SiC boules are provided that demonstrate reduced dislocation densities and improved dislocation uniformity across longer boule lengths. Corresponding SiC wafers include reduced total dislocation density (TDD) values and improved TDD radial uniformity. Growth conditions for SiC crystalline materials include providing source materials in oversaturated quantities where amounts of the source materials present during growth are significantly higher than what would typically be required. Such SiC crystalline materials and related methods are suitable for providing large diameter SiC boules and corresponding SiC wafers with improved crystalline quality.