公开(公告)号：US08507298B2

公开(公告)日：2013-08-13

申请号：US13310318

申请日：2011-12-02

申请人： Deepak A. Ramappa

发明人： Deepak A. Ramappa

IPC分类号： H01L21/00

CPC分类号： H01L31/0682 ,  H01L21/76802 ,  H01L31/022441 ,  Y02E10/547

摘要： At least part of a dielectric layer is implanted to form implanted regions. The implanted regions affect the etch rate of the dielectric layer during the formation of the openings through the dielectric layer. Metal contacts may be formed within these openings. The dielectric layer, which may be SiO2 or other materials, may be part of a solar cell or other device.

摘要翻译： 介电层的至少一部分被植入以形成植入区域。 注入区域在通过电介质层形成开口期间影响电介质层的蚀刻速率。 可以在这些开口内形成金属接触。 可以是SiO 2或其它材料的电介质层可以是太阳能电池或其他器件的一部分。

公开(公告)号：US20130064989A1

公开(公告)日：2013-03-14

申请号：US13608709

申请日：2012-09-10

申请人： Christopher R. Hatem ,  Ludovic Godet ,  Louis Steen ,  Deepak A. Ramappa

发明人： Christopher R. Hatem ,  Ludovic Godet ,  Louis Steen ,  Deepak A. Ramappa

IPC分类号： C23C14/48

CPC分类号： C23C14/048 ,  H01J37/32412

摘要： A surface of an insulating workpiece is implanted to form either hydrophobic or hydrophilic implanted regions. A conductive coating is deposited on the workpiece. The coating may be a polymer in one instance. This coating preferentially forms either on the implanted regions if these implanted regions are hydrophilic or on the non-implanted regions if the implanted regions are hydrophobic.

摘要翻译： 植入绝缘工件的表面以形成疏水或亲水注入区域。 导电涂层沉积在工件上。 在一种情况下，涂层可以是聚合物。 如果这些注入区域是亲水的，则该涂层优选地形成在注入区域上，或者如果注入的区域是疏水的，则优选地形成在非注入区域上。

公开(公告)号：US07868306B2

公开(公告)日：2011-01-11

申请号：US12243992

申请日：2008-10-02

申请人： Deepak A. Ramappa

发明人： Deepak A. Ramappa

IPC分类号： H01J37/317 ,  H01L21/265

CPC分类号： H01L21/26513 ,  H01L21/2253 ,  H01L21/2658 ,  H01L21/26593 ,  H01L21/31155 ,  H01L21/32155 ,  H01L21/324

摘要： A method for ion implantation is disclosed which includes modulating the temperature of the substrate during the implant process. This modulation affects the properties of the substrate, and can be used to minimize EOR defects, selectively segregate and diffuse out secondary dopants, maximize or minimize the amorphous region, and vary other semiconductor parameters. In one particular embodiment, a combination of temperature modulated ion implants are used. Ion implantation at higher temperatures is used in sequence with regular baseline processing and with ion implantation at cold temperatures. The temperature modulation could be at the beginning or at the end of the process to alleviate the detrimental secondary dopant effects.

摘要翻译： 公开了一种用于离子注入的方法，其包括在植入过程期间调制衬底的温度。 该调制影响衬底的性质，并且可以用于使EOR缺陷最小化，选择性地分离和扩散次级掺杂剂，使非晶区域最大化或最小化，并改变其它半导体参数。 在一个特定实施例中，使用温度调制离子植入物的组合。 在较高温度下的离子注入按照常规基线处理顺序使用，并在低温下进行离子注入。 温度调制可以在该过程的开始或结束时以减轻有害的二次掺杂剂效应。

公开(公告)号：US20100323113A1

公开(公告)日：2010-12-23

申请号：US12487100

申请日：2009-06-18

申请人： Deepak A. Ramappa ,  Paul Sullivan

发明人： Deepak A. Ramappa ,  Paul Sullivan

IPC分类号： B05D3/00

CPC分类号： C23C14/0605 ,  C23C14/48 ,  C23C14/5806

摘要： A method of using ion implantation techniques to create graphene is disclosed. Carbon ions are implanted in a substrate, such as a metal foil, using a plasma doping system or a beam line implanter. The implant is performed at an elevated temperature, to allow a large number of carbon ions to be absorbed by the foil. As the temperature is reduced, the excessive number of carbon atoms causes the foil to be saturated, and the carbon atoms diffuse to the surface, thereby producing graphene. In another embodiment, a plasma doping system is used, where a plasma containing carbon and other species is created. These additional species are also implanted, thereby causing the diffused atoms to contain both carbon and the additional species.

摘要翻译： 公开了一种使用离子注入技术制造石墨烯的方法。 使用等离子体掺杂系统或束线注入机将碳离子注入诸如金属箔的衬底中。 植入物在升高的温度下进行，以允许大量的碳离子被箔吸收。 当温度降低时，碳原子数过多会导致箔饱和，碳原子扩散到表面，从而产生石墨烯。 在另一个实施例中，使用等离子体掺杂系统，其中产生含有碳和其它物质的等离子体。 这些另外的物质也被植入，从而使扩散的原子含有碳和另外的物质。

公开(公告)号：US20100084580A1

公开(公告)日：2010-04-08

申请号：US12243992

申请日：2008-10-02

申请人： Deepak A. Ramappa

发明人： Deepak A. Ramappa

IPC分类号： H01J37/08

CPC分类号： H01L21/26513 ,  H01L21/2253 ,  H01L21/2658 ,  H01L21/26593 ,  H01L21/31155 ,  H01L21/32155 ,  H01L21/324

摘要： A method for ion implantation is disclosed which includes modulating the temperature of the substrate during the implant process. This modulation affects the properties of the substrate, and can be used to minimize EOR defects, selectively segregate and diffuse out secondary dopants, maximize or minimize the amorphous region, and vary other semiconductor parameters. In one particular embodiment, a combination of temperature modulated ion implants are used. Ion implantation at higher temperatures is used in sequence with regular baseline processing and with ion implantation at cold temperatures. The temperature modulation could be at the beginning or at the end of the process to alleviate the detrimental secondary dopant effects.

摘要翻译： 公开了一种用于离子注入的方法，其包括在植入过程期间调制衬底的温度。 该调制影响衬底的性质，并且可以用于使EOR缺陷最小化，选择性地分离和扩散次级掺杂剂，使非晶区域最大化或最小化，并改变其它半导体参数。 在一个特定实施例中，使用温度调制离子植入物的组合。 在较高温度下的离子注入按照常规基线处理顺序使用，并在低温下进行离子注入。 温度调制可以在该过程的开始或结束时以减轻有害的二次掺杂剂效应。

公开(公告)号：US20090212793A1

公开(公告)日：2009-08-27

申请号：US12037687

申请日：2008-02-26

申请人： Richard L. Guldi ,  Toan Tran ,  Deepak A. Ramappa

发明人： Richard L. Guldi ,  Toan Tran ,  Deepak A. Ramappa

IPC分类号： G01R31/305 ,  H01L23/58

CPC分类号： H01L22/14 ,  G01R31/2884 ,  G01R31/307 ,  H01L22/20 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for detecting defects during semiconductor device processing can include providing a substrate having a semiconductor comprising layer with electrically isolated application and test circuits are formed thereon, directing an electron current inducing beam to the test circuit; measuring a current between the first and the second contact pads in the test circuit; determining an electron beam induced current (EBIC); and identifying one or more defect locations in the test circuit based on the EBIC and a location of the electron beam corresponding to the EBIC. A test circuit can include a plurality of semiconductor devices connected in parallel, a first contact pad coupled to a first terminal of the semiconductor devices, and at least a second contact pad coupled to a substrate terminal associated with the semiconductor devices.

摘要翻译： 用于在半导体器件处理期间检测缺陷的方法可以包括提供具有电隔离应用的具有半导体层的衬底，并且在其上形成测试电路，将电子电流感应束引导到测试电路; 测量测试电路中的第一和第二接触焊盘之间的电流; 确定电子束感应电流（EBIC）; 以及基于EBIC和对应于EBIC的电子束的位置来识别测试电路中的一个或多个缺陷位置。 测试电路可以包括并联连接的多个半导体器件，耦合到半导体器件的第一端子的第一接触焊盘以及耦合到与半导体器件相关联的衬底端子的至少第二接触焊盘。

公开(公告)号：US07228193B2

公开(公告)日：2007-06-05

申请号：US11204143

申请日：2005-08-15

申请人： Richard L. Guldi ,  Jae H. Park ,  Deepak A. Ramappa

发明人： Richard L. Guldi ,  Jae H. Park ,  Deepak A. Ramappa

IPC分类号： G06F19/00

CPC分类号： G03F7/7065

摘要： Semiconductor devices formed on wafers are inspected using a master wafer. A subject wafer of a semiconductor design is provided. The subject wafer has dies wherein semiconductor devices of the semiconductor design are formed and at a stage of fabrication. A current layer of the subject wafer is scanned to obtain a scanned layer/image. A master wafer comprising individual wafer/layer maps is obtained. The scanned layer is compared with a corresponding layer map. Matching and non-matching defects are identified from repetitive defects within the corresponding layer map and defects within the scanned layer. The matching defects are reviewed to classify and or identify causality. The master wafer is then updated.

公开(公告)号：US07200498B2

公开(公告)日：2007-04-03

申请号：US10853867

申请日：2004-05-26

申请人： Deepak A. Ramappa

发明人： Deepak A. Ramappa

IPC分类号： G06F19/00

CPC分类号： H01L22/20 ,  Y10S438/935

摘要： The present invention defines a system (100) for detecting copper contamination within a semiconductor manufacturing process. According to the present invention, a semiconductor wafer (102) is transferred (108) from a semiconductor manufacturing component (104), which may have exposed the wafer to copper contamination, to a measurement system (106). The measurement system measures an electrical value at a plurality of locations along a surface of the wafer, prior to and after exposure of the surface to an activation system (112). The activation system is provided to cause any copper contamination along the surface to form a precipitate thereon. An analysis component (110) is provided to receive electrical value and location information from the measurement system and to identify, from the measurements, the presence and location of copper contamination along the semiconductor wafer surface.

摘要翻译： 本发明定义了一种在半导体制造过程中检测铜污染的系统（100）。 根据本发明，将半导体制造部件（104）从半导体制造部件（104）转移（108），半导体制造部件（104）可能将晶片暴露于铜污染物到测量系统（106）。 测量系统在将表面暴露于激活系统（112）之前和之后，测量沿着晶片表面的多个位置处的电气值。 提供激活系统以使沿着表面的任何铜污染物在其上形成沉淀物。 提供分析组件（110）以从测量系统接收电值和位置信息，并从测量中识别沿着半导体晶片表面的铜污染的存在和位置。

公开(公告)号：US20140038393A1

公开(公告)日：2014-02-06

申请号：US13563056

申请日：2012-07-31

申请人： Ludovic Godet ,  Xianfeng Lu ,  Deepak A. Ramappa

发明人： Ludovic Godet ,  Xianfeng Lu ,  Deepak A. Ramappa

IPC分类号： C23C16/50 ,  B05C9/00 ,  H01L21/203 ,  B44C1/22

CPC分类号： H01J37/32366 ,  C23C16/04 ,  C23C16/50 ,  H01J37/3056 ,  H01J37/3178 ,  H01J2237/08 ,  H01J2237/31732

摘要： A method of processing a substrate includes performing a first exposure that comprises generating a plasma containing reactive gas ions in a plasma chamber and generating a bias voltage between the substrate and the plasma chamber. The method also includes providing a plasma sheath modifier having an aperture disposed between the plasma and substrate and operable to direct the reactive gas ions toward the substrate, and establishing a pressure differential between the plasma chamber and substrate region while the reactive gas ions are directed onto the substrate.

摘要翻译： 一种处理衬底的方法包括执行第一曝光，其包括在等离子体室中产生含有反应气体离子的等离子体，并在衬底和等离子体室之间产生偏置电压。 该方法还包括提供等离子体护套改性剂，其具有设置在等离子体和衬底之间的孔，并可操作以将反应性气体离子引向衬底，并且在反应性气体离子被引导到等离子体室和衬底区域之间建立压力差 底物。

公开(公告)号：US08461030B2

公开(公告)日：2013-06-11

申请号：US12947078

申请日：2010-11-16

申请人： Anthony Renau ,  Ludovic Godet ,  Timothy J. Miller ,  Joseph C. Olson ,  Vikram Singh ,  James Buonodono ,  Deepak A. Ramappa ,  Russell J. Low ,  Atul Gupta ,  Kevin M. Daniels

发明人： Anthony Renau ,  Ludovic Godet ,  Timothy J. Miller ,  Joseph C. Olson ,  Vikram Singh ,  James Buonodono ,  Deepak A. Ramappa ,  Russell J. Low ,  Atul Gupta ,  Kevin M. Daniels

IPC分类号： H01L21/26 ,  H01L21/42

CPC分类号： B01J19/081 ,  H01J37/3171 ,  H01J37/32357 ,  H01J37/32422 ,  H01J37/32623 ,  H01J2237/0453 ,  H01J2237/1205 ,  H01L21/2236 ,  H01L31/022425 ,  H01L31/068 ,  H01L31/08 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： A plasma processing apparatus comprises a plasma source configured to produce a plasma in a plasma chamber, such that the plasma contains ions for implantation into a workpiece. The apparatus also includes a focusing plate arrangement having an aperture arrangement configured to modify a shape of a plasma sheath of the plasma proximate the focusing plate such that ions exiting an aperture of the aperture arrangement define focused ions. The apparatus further includes a processing chamber containing a workpiece spaced from the focusing plate such that a stationary implant region of the focused ions at the workpiece is substantially narrower that the aperture. The apparatus is configured to create a plurality of patterned areas in the workpiece by scanning the workpiece during ion implantation.