公开(公告)号：US08415712B2

公开(公告)日：2013-04-09

申请号：US12648847

申请日：2009-12-29

Applicant: Florin Udrea ,  Vasantha Pathirana ,  Tanya Trajkovic ,  Nishad Udugampola

Inventor： Florin Udrea ,  Vasantha Pathirana ,  Tanya Trajkovic ,  Nishad Udugampola

IPC: H01L29/739 ,  H01L21/331

CPC classification number: H01L29/7394 ,  H01L29/402

Abstract: This invention generally relates to LIGBTs, ICs comprising an LIGBT and methods of forming an LIGBT, and more particularly to an LIGBT comprising a substrate region of first conductivity type and peak dopant concentration less than about 1×1017/cm3; a lateral drift region of a second, opposite conductivity type adjacent the substrate region and electrically coupled to said substrate region; a charge injection region of the first conductivity type to inject charge toward said lateral drift region; a gate to control flow of said charge in said lateral drift region; metal enriched adhesive below said substrate region; and an intermediate layer below said substrate region to substantially suppress charge injection into said substrate region from said metal enriched adhesive.

Abstract translation: 本发明一般涉及LIGBT，包含LIGBT的IC和形成LIGBT的方法，更具体地涉及包含第一导电类型的衬底区域和小于约1×1017 / cm3的峰值掺杂剂浓度的LIGBT; 邻近所述衬底区域的第二相反导电类型的横向漂移区域，并电耦合到所述衬底区域; 第一导电类型的电荷注入区域，用于向所述横向漂移区域注入电荷; 用于控制所述横向漂移区域中的所述电荷的流动的门; 在所述衬底区域下面的富含金属的粘合剂; 以及在所述衬底区域下面的中间层，以基本上抑制从所述金属富集粘合剂向所述衬底区域注入电荷。

公开(公告)号：US20130069712A1

公开(公告)日：2013-03-21

申请号：US13233672

申请日：2011-09-15

Applicant: Tanya Trajkovic ,  Florin Udrea ,  Vasantha Pathirana ,  Nishad Udugampola

Inventor： Tanya Trajkovic ,  Florin Udrea ,  Vasantha Pathirana ,  Nishad Udugampola

IPC: H01L29/78 ,  G05F3/02 ,  H01L21/336

CPC classification number: H01L29/0634 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66325 ,  H01L29/66681 ,  H01L29/7393 ,  H01L29/7816 ,  H01L29/7824 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: We describe a RESURF semiconductor device having an n-drift region with a p-top layer and in which a MOS (Metal Oxide Semiconductor) channel of the device is formed within the p-top layer.

Abstract translation: 我们描述了具有p顶层的n-漂移区的RESURF半导体器件，并且其中在该p顶层中形成该器件的MOS（金属氧化物半导体）沟道。

公开(公告)号：US20110254050A1

公开(公告)日：2011-10-20

申请号：US12760754

申请日：2010-04-15

Applicant: Florin Udrea ,  Chih-Wei Hsu ,  Wei-Chieh Lin

Inventor： Florin Udrea ,  Chih-Wei Hsu ,  Wei-Chieh Lin

IPC: H01L29/74 ,  H01L21/332

CPC classification number: H01L29/7397 ,  H01L29/0834 ,  H01L29/66348

Abstract: An insulated gate bipolar transistor (IGBT) is provided comprising a semiconductor substrate having the following regions in sequence: (i) a first region of a first conductive type having opposing surfaces, a column region of a second conductive type within the first region extending from a first of said opposing surfaces; (ii) a drift region of the second conductive type; (iii) a second region of the first conductive type, and (iv) a third region of the second conductive type. There is provided a gate electrode disposed to form a channel between the third region and the drift region, a first electrode operatively connected to the second region and the third region, a second electrode operatively connected to the first region and the column region. The arrangement of the IGBT is such that the column region is spaced from a second surface of the opposing surfaces of the first region, whereby a forward conduction path extends sequentially through the third region, the second region, the drift region, and the first region, and whereby a reverse conduction path extends sequentially through the second region, the drift region, the first region and the column region. Reverse conduction of the IGBT occurs through a thyristor structure which is embedded in the IGBT. Such an IGBT structure is advantageous over a reverse conducting IGBT structure in which an anti-parallel diode is integrated or embedded because it provides improved reverse conduction and snapback performance.

Abstract translation: 提供了绝缘栅双极晶体管（IGBT），其包括依次具有以下区域的半导体衬底：（i）具有相对表面的第一导电类型的第一区域，在第一区域内延伸的第二导电类型的列区域 所述相对表面中的第一个; （ii）第二导电类型的漂移区域; （iii）第一导电类型的第二区域，和（iv）第二导电类型的第三区域。 提供了一个设置成在第三区域和漂移区域之间形成通道的栅电极，可操作地连接到第二区域和第三区域的第一电极，可操作地连接到第一区域和列区域的第二电极。 IGBT的布置使得列区域与第一区域的相对表面的第二表面间隔开，由此正向导电路径依次延伸穿过第三区域，第二区域，漂移区域和第一区域 并且由此反向传导路径依次延伸穿过第二区域，漂移区域，第一区域和列区域。 IGBT的反向导通通过嵌入在IGBT中的晶闸管结构发生。 这种IGBT结构优于反并联二极管集成或嵌入的反向导通IGBT结构，因为它提供改进的反向导通和快速恢复性能。

公开(公告)号：US20090058498A1

公开(公告)日：2009-03-05

申请号：US11847234

申请日：2007-08-29

Applicant: Florin UDREA ,  Nishad Udugampola ,  Gehan Anil Joseph Amaratunga

Inventor： Florin UDREA ,  Nishad Udugampola ,  Gehan Anil Joseph Amaratunga

IPC: H03K17/56 ,  H03K17/74

CPC classification number: H03K17/567 ,  H01L29/0638 ,  H01L29/7393 ,  H03K17/08142 ,  H03K17/6871 ,  H03K2017/6878

Abstract: A half bridge circuit has a first switch having at least one control gate and a second switch having at least two control gates. A first driver has an output connected to a control gate of the first switch. A second driver has an output connected to a first control gate of the second switch. The output of the first driver is connected to a second control gate of the second switch by a circuit arrangement such that when the first driver is operated to apply a high, positive voltage to the control gate of the first switch, a positive voltage is applied to the second control gate of the second switch, and such that when the first driver is operated to apply a low, zero or small voltage to the control gate of the first switch, a negative voltage is applied to said second control gate of the second switch.

Abstract translation: 半桥电路具有具有至少一个控制栅极的第一开关和具有至少两个控制栅极的第二开关。 第一驱动器具有连接到第一开关的控制栅极的输出端。 第二驱动器具有连接到第二开关的第一控制栅极的输出。 第一驱动器的输出通过电路装置连接到第二开关的第二控制栅极，使得当第一驱动器被操作以向第一开关的控制栅极施加高正正电压时，施加正电压 并且使得当第一驱动器被操作以向第一开关的控制栅极施加低，零或小的电压时，负电压被施加到第二开关的第二控制栅极的第二控制栅极 开关。

公开(公告)号：US20080012043A1

公开(公告)日：2008-01-17

申请号：US11486377

申请日：2006-07-14

Applicant: Florin Udrea ,  Nishad Udugampola ,  Gehan A.J. Amaratunga

Inventor： Florin Udrea ,  Nishad Udugampola ,  Gehan A.J. Amaratunga

IPC: H01L29/74 ,  H01L29/45 ,  H01L29/76

CPC classification number: H01L29/7393 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/4232 ,  H01L29/7394 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A bipolar high voltage/power semiconductor device has a drift region having adjacent its ends regions of different conductivity types respectively. High and low voltage terminals are provided. A first insulated gate terminal and a second insulated gate terminal are also provided. One or more drive circuits provide appropriate voltages to the first and second insulated gate terminals so as to allow current conduction in a first direction or in a second direction that is opposite the first direction.

Abstract translation: 双极型高压/功率半导体器件具有分别具有与其不同导电类型的端部区域相邻的漂移区域。 提供高低压端子。 还提供了第一绝缘栅极端子和第二绝缘栅极端子。 一个或多个驱动电路为第一和第二绝缘栅极端子提供适当的电压，以允许在与第一方向相反的第一方向或第二方向上的电流传导。

公开(公告)号：US07230314B2

公开(公告)日：2007-06-12

申请号：US10400541

申请日：2003-03-28

Applicant: Florin Udrea ,  Gehan A. J. Amaratunga

Inventor： Florin Udrea ,  Gehan A. J. Amaratunga

IPC: H01L21/00

CPC classification number: H01L23/3735 ,  H01L21/84 ,  H01L2924/0002 ,  H01L2924/10158 ,  H01L2924/00

Abstract: A semiconductor device having an active region is formed in a layer provided on a semiconductor substrate. At least a portion of the semiconductor substrate below at least a portion of the active region is removed such that the portion of the active region is provided in a membrane defined by that portion of the layer below which the semiconductor substrate has been removed. A heat conducting and electrically insulating layer is applied to the bottom surface of the membrane. The heat conducting and electrically insulating layer has a thermal conductivity that is higher than the thermal conductivity of the membrane so that the heat conducting and electrically insulating layer allows heat to pass from the active region into the heat conducting and electrically insulating layer during normal operation of the device.

Abstract translation: 具有有源区的半导体器件形成在设置在半导体衬底上的层中。 移除至少部分有源区的半导体衬底的至少一部分，使得有源区的一部分设置在由半导体衬底已被去除的层的该部分限定的膜中。 将导热和电绝缘层施加到膜的底表面。 导热和电绝缘层的导热率高于膜的热导率，使得导热和电绝缘层在正常操作期间允许热量从有源区域传导到导热和电绝缘层中 装置。

公开(公告)号：US20060197156A1

公开(公告)日：2006-09-07

申请号：US11414308

申请日：2006-05-01

Applicant: Gehan Joseph Amaratunga ,  Florin Udrea

Inventor： Gehan Joseph Amaratunga ,  Florin Udrea

IPC: H01L27/12

CPC classification number: H01L29/7824 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41725 ,  H01L29/4175 ,  H01L29/42368 ,  H01L29/78603 ,  H01L29/78624

Abstract: This invention is generally concerned with power semiconductors such as power MOS transistors, insulated gate by bipolar transistors (IGBTs), high voltage diodes and the like, and methods for their fabrication. A power semiconductor, the semiconductor comprising: a power device, said power device having first and second electrical contact regions and a drift region extending therebetween; and a semiconductor substrate mounting said device; and wherein said power semiconductor includes an electrically insulate, layer between said semiconductor substrate and said power device, said electrically insulating layer having a thickness of at least 5 μm.

Abstract translation: 本发明一般涉及诸如功率MOS晶体管，双极晶体管（IGBT）的绝缘栅极，高压二极管等功率半导体及其制造方法。 功率半导体，所述半导体包括：功率器件，所述功率器件具有第一和第二电接触区域和在其间延伸的漂移区域; 以及安装所述装置的半导体衬底; 并且其中所述功率半导体在所述半导体衬底和所述功率器件之间包括电绝缘层，所述电绝缘层具有至少5μm的厚度。

公开(公告)号：US20050145852A1

公开(公告)日：2005-07-07

申请号：US10995566

申请日：2004-11-24

Applicant: Rajesh Kumar ,  Yuichi Takeuchi ,  Mitsuhiro Kataoka ,  Suhail Jeremy ,  Andrei Mihaila ,  Florin Udrea

Inventor： Rajesh Kumar ,  Yuichi Takeuchi ,  Mitsuhiro Kataoka ,  Suhail Jeremy ,  Andrei Mihaila ,  Florin Udrea

IPC: H01L29/80 ,  H01L21/337 ,  H01L29/24 ,  H01L29/808 ,  H01L29/15

CPC classification number: H01L29/8083 ,  H01L29/1608

Abstract: A silicon carbide semiconductor device includes: a semiconductor substrate including first and second gate layers, a channel layer, a source layer, and a trench; a gate wiring having a first portion and a plurality of second portions; and a source wiring having a third portion and a plurality of fourth portions. The trench extends in a predetermined extending direction. The first portion connects to the first gate layer in the trench, and extends to the extending direction. The second portions protrude perpendicularly to be a comb shape. The third portion extends to the extending direction. The fourth portions protrude perpendicularly to be a comb shape, and electrically connect to the source layer. Each of the second portions connects to the second gate layer through a contact hole.

Abstract translation: 碳化硅半导体器件包括：包括第一和第二栅极层，沟道层，源极层和沟槽的半导体衬底; 栅极布线，具有第一部分和多个第二部分; 以及具有第三部分和多个第四部分的源极布线。 沟槽沿预定的延伸方向延伸。 第一部分连接到沟槽中的第一栅极层，并延伸到延伸方向。 第二部分垂直突出成为梳形。 第三部分延伸到延伸方向。 第四部分垂直突出成梳状，并且电连接到源层。 每个第二部分通过接触孔连接到第二栅极层。

公开(公告)号：US20050006716A1

公开(公告)日：2005-01-13

申请号：US10776338

申请日：2004-02-12

Applicant: Rajesh Kumar ,  Florin Udrea ,  Andrei Mihaila

Inventor： Rajesh Kumar ,  Florin Udrea ,  Andrei Mihaila

IPC: H01L21/04 ,  H01L21/337 ,  H01L21/8232 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/07 ,  H01L27/088 ,  H01L27/095 ,  H01L29/24 ,  H01L29/80 ,  H01L29/808 ,  H01L29/00

CPC classification number: H01L29/66068 ,  H01L27/0705 ,  H01L27/088 ,  H01L29/1608 ,  H01L29/808 ,  H01L29/8083

Abstract: A semiconductor device includes a first field effect transistor including a source and a gate and disposed in a silicon carbide substrate; and a second field effect transistor including a drain and a gate and disposed in the substrate. The drain of the second field effect transistor connects to the source of the first field effect transistor. The gate of the second field effect transistor connects to the gate of the first field effect transistor.

Abstract translation: 半导体器件包括：第一场效应晶体管，其包括源极和栅极，并设置在碳化硅衬底中; 以及包括漏极和栅极并设置在所述衬底中的第二场效应晶体管。 第二场效应晶体管的漏极连接到第一场效应晶体管的源极。 第二场效应晶体管的栅极连接到第一场效应晶体管的栅极。

公开(公告)号：US06693340B1

公开(公告)日：2004-02-17

申请号：US09870040

申请日：2001-05-30

Applicant: Gehan Anil Joseph Amaratunga ,  Ranick Kian Ming Ng ,  Florin Udrea

Inventor： Gehan Anil Joseph Amaratunga ,  Ranick Kian Ming Ng ,  Florin Udrea

IPC: H01L2358

CPC classification number: H01L29/0634 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/41758 ,  H01L29/7824 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A lateral semiconductor device has a semiconductor layer on an insulating layer on a semiconductor substrate. The semiconductor layer has a region of a first conduction type and a region of a second conduction type with a drift region therebetween. The drift region is provided by a region of the first conduction type and a region of the second conduction type. The first and second conduction type drift regions are so arranged that when a reverse voltage bias is applied across the first and second conduction type regions of the semiconductor layer, the second conduction type drift region has an excess of charge relative to the first conduction type drift region which varies substantially linearly from the end of the drift region towards the first conduction type region of the semiconductor layer to the end of the drift region towards the second conduction type region of the semiconductor layer.

Abstract translation: 横向半导体器件在半导体衬底上的绝缘层上具有半导体层。 半导体层具有第一导电类型的区域和具有漂移区域的第二导电类型的区域。 漂移区域由第一导电类型的区域和第二导电类型的区域提供。 第一和第二导电类型漂移区域被布置成使得当跨越半导体层的第一和第二导电类型区域施加反向电压偏压时，第二导电类型漂移区域相对于第一导电类型漂移具有过量的电荷 区域，其从漂移区域的端部朝向半导体层的第一导电类型区域到漂移区域的端部朝向半导体层的第二导电类型区域基本上线性地变化。