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55 条记录 (耗时 0.018 秒)

    Auto power down circuit for a semiconductor memory device
    21.
    发明授权
    Auto power down circuit for a semiconductor memory device 失效
    半导体存储器件的自动断电电路

    公开(公告)号：US5905688A

    公开(公告)日：1999-05-18

    申请号：US30844

    申请日：1998-02-26

    申请人： Jong-Hoon Park

    发明人： Jong-Hoon Park

    IPC分类号： G11C11/41 ,  G11C11/413 ,  G11C11/417 ,  G11C29/06 ,  G11C29/50 ,  G11C7/00

    CPC分类号： G11C11/417 ,  G11C29/50 ,  G11C11/41

    摘要： A power down circuit for a memory device is provided that includes a burn-in voltage detector to generate a burn-in voltage detecting signal to control a power down signal when a burn-in voltage reaches a predetermined level. The power down circuit enhances a burn-in function by operating the memory cells and peripheral circuits for a relatively long time at a high level voltage when a burn-in is performed on the memory device with an auto power down function. Thus, the memory device reliability is also enhanced. The memory device includes a power down timer for generating a power down signal to control an input/output operation of a memory cell in response to a plurality of address transition detecting signals, a plurality of data input detecting signals, a chip select detecting signal, a write mode detecting signal and the burn-in voltage detecting signal.

    摘要翻译： 提供一种用于存储器件的掉电电路，其包括老化电压检测器，以在老化电压达到预定电平时产生老化电压检测信号，以控制掉电信号。 断电电路通过在具有自动关机功能的存储器件上进行老化时以高电平电压操作存储器单元和外围电路相当长的时间来增强老化功能。 因此，存储器件的可靠性也得到提高。 该存储装置包括一个断电定时器，用于响应于多个地址转换检测信号，多个数据输入检测信号，芯片选择检测信号，产生掉电信号来控制存储器单元的输入/输出操作， 写入模式检测信号和老化电压检测信号。

    Wire control circuit and method
    22.
    发明授权
    Wire control circuit and method 失效
    写控制电路和方法

    公开(公告)号：US5818767A

    公开(公告)日：1998-10-06

    申请号：US895448

    申请日：1997-07-16

    申请人： Kyung-Yul Kim ,  Jong-Hoon Park

    发明人： Kyung-Yul Kim ,  Jong-Hoon Park

    IPC分类号： G11C11/417 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C11/409

    CPC分类号： G11C7/1078 ,  G11C7/22

    摘要： A write control circuit performs write control of data in a write cycle using consistent parametric control according to a control signal and a write enable signal. A first buffer outputs a buffered control signal based on the control signal, and a second buffer outputs a buffered write enable signal based on the buffered control signal from the first buffer and the write enable signal. A write controller detects an input condition of the control signal and the write enable signal and outputs a delay control signal. A write control signal generator selects a delayed signal based on the delay control signal from the write controller and generates a write control signal, and an output unit outputs input data to data lines in accordance with the generated write control signal.

    摘要翻译： 写控制电路根据控制信号和写使能信号，使用一致的参数控制来执行写周期中数据的写控制。 第一缓冲器基于控制信号输出缓冲的控制信号，并且第二缓冲器基于来自第一缓冲器的缓冲控制信号和写使能信号输出缓冲写使能信号。 写入控制器检测控制信号和写使能信号的输入条件，并输出延迟控制信号。 写入控制信号发生器基于来自写入控制器的延迟控制信号选择延迟信号，并产生写入控制信号，并且输出单元根据生成的写入控制信号将输入数据输出到数据线。

    Pulse extending circuit
    23.
    发明授权
    Pulse extending circuit 失效
    脉冲扩展电路

    公开(公告)号：US5682113A

    公开(公告)日：1997-10-28

    申请号：US534973

    申请日：1995-09-27

    申请人： Jong Hoon Park ,  Jae Woon Kim

    发明人： Jong Hoon Park ,  Jae Woon Kim

    IPC分类号： H03K5/04 ,  H03K3/017

    CPC分类号： H03K5/04

    摘要： A pulse extending circuit includes a pulse extension inverting device for extending an input pulse signal by a predetermined width; and a delay device for extending the signal output from the pulse extension inverting device; thereby increasing a delay effect.

    摘要翻译： 脉冲延迟电路包括用于将输入脉冲信号延伸预定宽度的脉冲延伸反转装置; 以及延迟装置，用于延长从脉冲延伸反转装置输出的信号; 从而增加延迟效应。

    Transmission-line transformer in which signal efficiency is maximised
    24.
    发明授权
    Transmission-line transformer in which signal efficiency is maximised 有权
    传输线变压器信号效率最大化

    公开(公告)号：US09246206B2

    公开(公告)日：2016-01-26

    申请号：US13824012

    申请日：2011-09-07

    申请人： Jong Hoon Park ,  Chang Kun Park

    发明人： Jong Hoon Park ,  Chang Kun Park

    IPC分类号： H01P5/12 ,  H01F19/00 ,  H01P5/10 ,  H01F17/00 ,  H01P5/04

    CPC分类号： H01P5/12 ,  H01F17/0006 ,  H01F19/00 ,  H01P5/04 ,  H01P5/10

    摘要： Provided is a transmission line transformer having increased signal efficiency. The transmission line transformer is formed on an integrated circuit (IC), wherein a first transmission line disposed in one direction. Second and third transmission lines have same length direction as the first transmission line and are spaced apart from each other in a lateral direction above or below the first transmission line. Accordingly, an area of the first transmission line and areas of the second and third transmission lines, which face each other, are increased, thereby improving a coupling factor. Also, since a secondary transmission line is divided into two regions and uses the second and third transmission lines that have narrower widths than the first transmission line, parasitic capacitance components generated between the first through third transmission lines and a semiconductor substrate may be decreased.

    摘要翻译： 提供了具有增加的信号效率的传输线变压器。 传输线变压器形成在集成电路（IC）上，其中沿一个方向布置的第一传输线。 第二传输线和第三传输线具有与第一传输线相同的长度方向，并且在第一传输线上方或下方的横向方向彼此间隔开。 因此，第一传输线的面积和彼此相对的第二和第三传输线的面积增加，从而提高耦合系数。 此外，由于二次传输线被分成两个区域并且使用具有比第一传输线窄的宽度的第二和第三传输线，所以可以减少在第一至第三传输线和半导体衬底之间产生的寄生电容分量。

    Combination-type transistor and method for manufacturing same
    25.
    发明授权
    Combination-type transistor and method for manufacturing same 有权
    组合型晶体管及其制造方法

    公开(公告)号：US09159628B2

    公开(公告)日：2015-10-13

    申请号：US14361708

    申请日：2012-05-15

    申请人： Jong Hoon Park ,  Chang Kun Park

    发明人： Jong Hoon Park ,  Chang Kun Park

    IPC分类号： H01L21/8238 ,  H01L27/06 ,  H01L27/07 ,  H01L21/8228

    CPC分类号： H01L21/8238 ,  H01L21/8228 ,  H01L27/0623 ,  H01L27/0705

    摘要： Disclosed is a combination-type transistor including a first MOSFET that includes a gate, a first source formed on one side of the gate, and a first drain formed on the other side of the gate; a second MOSFET that includes the gate, a second drain formed on the one side of the gate, and a second source formed on the other side of the gate; a first BJT that is formed such that the first source of the first MOSFET is used as an emitter, the second drain of the second MOSFET is used as a collector, and the substrate is used as a base; and a second BJT that is formed such that the second source of the second MOSFET is used as an emitter, the first drain of the first MOSFET is used as a collector, and the substrate is used as a base.

    摘要翻译： 公开了一种组合型晶体管，其包括：第一MOSFET，其包括栅极，形成在栅极一侧的第一源极和形成在栅极的另一侧上的第一漏极; 包括栅极的第二MOSFET，形成在栅极一侧的第二漏极和形成在栅极另一侧的第二源极; 第一BJT被形成为使得第一MOSFET的第一源用作发射极，第二MOSFET的第二漏极用作集电极，并且将衬底用作基极; 以及第二BJT，其被形成为使得第二MOSFET的第二源用作发射极，第一MOSFET的第一漏极用作集电极，并且将衬底用作基极。

    Semiconductor wafer and fabrication method of a semiconductor chip
    27.
    发明授权
    Semiconductor wafer and fabrication method of a semiconductor chip 有权
    半导体晶片及半导体芯片的制造方法

    公开(公告)号：US06531709B1

    公开(公告)日：2003-03-11

    申请号：US09715058

    申请日：2000-11-20

    申请人： Jae Woon Kim ,  Jong Hoon Park

    发明人： Jae Woon Kim ,  Jong Hoon Park

    IPC分类号： H01L2358

    CPC分类号： H01L24/05 ,  H01L21/78 ,  H01L22/32 ,  H01L23/528 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/0392 ,  H01L2224/05599 ,  H01L2924/01004 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/00014

    摘要： The present invention relates to a semiconductor device, and more particularly to a structure of a semiconductor wafer and a fabrication method of semiconductor chips. According to the present invention, a semiconductor wafer containing a plurality of semiconductor chip portions has a plurality of chip scribe lanes formed between the semiconductor chip portions. A plurality of chip bonding pads are formed on the semiconductor chip portions of the wafer, and a plurality of wafer probing pads are formed on the chip scribe lanes. The wafer probing pads are electrically connected to internal circuits of the semiconductor chip portions and/or to corresponding ones of the chip bonding pads.

    摘要翻译： 半导体器件技术领域本发明涉及半导体器件，更具体地，涉及半导体晶片的结构和半导体芯片的制造方法。 根据本发明，包含多个半导体芯片部分的半导体晶片在半导体芯片部分之间形成有多个芯片划线。 在晶片的半导体芯片部分上形成多个芯片接合焊盘，并且在芯片划线上形成多个晶片探测焊盘。 晶片探测焊盘电连接到半导体芯片部分的内部电路和/或与芯片焊盘的相应芯片电连接。

    Video window control apparatus and method thereof
    29.
    发明授权
    Video window control apparatus and method thereof 失效
    视窗控制装置及其方法

    公开(公告)号：US6069669A

    公开(公告)日：2000-05-30

    申请号：US770199

    申请日：1996-12-19

    申请人： Jong-Hoon Park ,  Jin-Sang Choi ,  Seon-Ja Kim ,  Kyeong-Yeol Yu ,  Dae-Hwan Hwang

    发明人： Jong-Hoon Park ,  Jin-Sang Choi ,  Seon-Ja Kim ,  Kyeong-Yeol Yu ,  Dae-Hwan Hwang

    IPC分类号： G06F3/14 ,  G09G5/14 ,  G09G5/395 ,  H04N5/445 ,  H04N5/45 ,  H04N9/74 ,  H04N9/76 ,  H04N9/268

    CPC分类号： H04N5/45 ,  G09G5/14 ,  H04N21/4316 ,  H04N5/44591 ,  G09G2340/125 ,  G09G5/395

    摘要： An improved video window control apparatus and a method thereof which are capable of generating a plurality of video windows on a television or a computer monitor, controlling the size and position thereof, and providing a video window overlap function and a picture-in-picture function. The apparatus includes a video window flow control means for controlling the size based on an input control of a video window and a position and overlap of the video windows based on a video output control and for outputting a video windows input control signal, a video output control signal, and a video selection signal, a plurality of video memory means for receiving a video signal outputted from an external video input and processing means in accordance with the video input control signal and for limitedly outputting the video signals in accordance with a video output control signal, and a video combining means for combining the video signals from the video memory into one video signal in accordance with the video selection signal and for outputting the video signal to an external video output means.

    摘要翻译： 一种改进的视频窗口控制装置及其方法，其能够在电视或计算机监视器上产生多个视频窗口，控制其尺寸和位置，以及提供视频窗口重叠功能和画中画功能 。 该装置包括：视频窗口流控制装置，用于基于视频输出控制基于视频窗口的输入控制和视频窗口的位置和重叠来控制大小，并用于输出视频窗口输入控制信号，视频输出 控制信号和视频选择信号，多个视频存储装置，用于根据视频输入控制信号接收从外部视频输入端输出的视频信号和处理装置，并且根据视频输出限制输出视频信号 控制信号和视频组合装置，用于根据视频选择信号将来自视频存储器的视频信号组合成一个视频信号，并将视频信号输出到外部视频输出装置。

    Output buffer for memory circuit
    30.
    发明授权
    Output buffer for memory circuit 失效
    存储器电路的输出缓冲器

    公开(公告)号：US5959474A

    公开(公告)日：1999-09-28

    申请号：US000765

    申请日：1997-12-30

    申请人： Jong Hoon Park ,  Tae Hyung Jung

    发明人： Jong Hoon Park ,  Tae Hyung Jung

    IPC分类号： G11C7/10 ,  H03K19/003 ,  H03K3/00

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  H03K19/00361

    摘要： An output buffer circuit comprising a pull-up transistor, a pull-down transistor coupled to the pull-up transistor, a first voltage source for supplying a driving voltage, a second voltage source for supplying a reference voltage, a device for comparing the driving voltage with the reference voltage, a driving voltage detector for producing a signal in response to operation of the comparing device, first and second pull-up driving buffers, the first and second pull-up driving buffers being activated according to the signal from the driving voltage detector, the pull-up transistor being driven by one of the pull-up driving buffers, and first and second pull-down driving buffers, the first and second pull-down driving buffers being activated according to the signal from the driving voltage detector, and the pull-down transistor being driven by one of the pull-down driving buffers.

    摘要翻译： 一种输出缓冲电路，包括上拉晶体管，耦合到上拉晶体管的下拉晶体管，用于提供驱动电压的第一电压源，用于提供参考电压的第二电压源，用于比较驱动电压的装置 具有参考电压的电压;响应于比较装置的操作产生信号的驱动电压检测器，第一和第二上拉驱动缓冲器，第一和第二上拉驱动缓冲器根据来自驱动器的信号被激活 电压检测器，上拉晶体管由上拉驱动缓冲器中的一个以及第一和第二下拉驱动缓冲器驱动，第一和第二下拉驱动缓冲器根据来自驱动电压检测器的信号被激活 并且下拉晶体管由下拉驱动缓冲器之一驱动。