公开(公告)号：US20060229046A1

公开(公告)日：2006-10-12

申请号：US11432435

申请日：2006-05-12

Applicant: Klaas Bult ,  Rudy Plassche ,  Arnoldus Venes

Inventor： Klaas Bult ,  Rudy Plassche ,  Arnoldus Venes

IPC: H04B1/06 ,  H04B7/00

CPC classification number: H03G3/30 ,  H03F1/34 ,  H03F3/195 ,  H03F3/24 ,  H03F3/45188 ,  H03F3/45192 ,  H03F2200/294 ,  H03F2200/331 ,  H03F2200/372 ,  H03F2200/513 ,  H03F2203/45644 ,  H03G1/0029 ,  H04B2001/0433

Abstract: An integrated communications system. Comprising a substrate having a receiver disposed on the substrate for converting a received signal to an IF signal. Coupled to a VGA for low voltage applications and coupled to the receiver for processing the IF signal. The VGA includes a bank pair having a first bank of differential pairs of transistors and a second bank of differential pairs of transistors. The bank pair is cross-coupled in parallel, the IF signal is applied to the bank pair decoupled from a control signal used to control transconductance output gain of the bank pair over a range of input voltages. A digital IF demodulator is disposed on the substrate and coupled to the VGA for low voltage applications, for converting the IF signal to a demodulated baseband signal. And a transmitter is disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.

公开(公告)号：US20060192614A1

公开(公告)日：2006-08-31

申请号：US11345946

申请日：2006-02-02

Applicant: Arya Behzad ,  Klaas Bult ,  Ramon Gomez ,  Chi-Hung Lin ,  Tom Kwan ,  Oscar Agazzi ,  John Creigh ,  Mehdi Hatamian ,  David Kruse ,  Arthur Abnous ,  Henry Samueli

Inventor： Arya Behzad ,  Klaas Bult ,  Ramon Gomez ,  Chi-Hung Lin ,  Tom Kwan ,  Oscar Agazzi ,  John Creigh ,  Mehdi Hatamian ,  David Kruse ,  Arthur Abnous ,  Henry Samueli

IPC: H03B1/00

CPC classification number: H03F1/32 ,  H03F3/347 ,  H03F3/505 ,  H03F2200/211 ,  H03F2200/252 ,  H03F2200/421 ,  H03F2200/513 ,  H03G1/0088 ,  H03G3/001 ,  H03G3/3036 ,  H03G3/3052 ,  H03G5/10 ,  H03H11/245

Abstract: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

公开(公告)号：US07092043B2

公开(公告)日：2006-08-15

申请号：US09439101

申请日：1999-11-12

Applicant: Pieter Vorenkamp ,  Klaas Bult ,  Frank Carr ,  Christopher M. Ward ,  Ralph Duncan ,  Tom W. Kwan ,  James Y. C. Chang ,  Haideh Khorramabadi

Inventor： Pieter Vorenkamp ,  Klaas Bult ,  Frank Carr ,  Christopher M. Ward ,  Ralph Duncan ,  Tom W. Kwan ,  James Y. C. Chang ,  Haideh Khorramabadi

IPC: H04N5/455

CPC classification number: H03D3/18 ,  H01F17/0006 ,  H01F17/0013 ,  H01F27/34 ,  H01F27/40 ,  H01F27/42 ,  H01F2017/0053 ,  H01F2021/125 ,  H01L23/5227 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03B5/04 ,  H03B5/364 ,  H03D7/161 ,  H03D7/18 ,  H03F1/26 ,  H03F1/3211 ,  H03F3/195 ,  H03F3/45183 ,  H03F3/45188 ,  H03F3/68 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2200/447 ,  H03F2200/63 ,  H03F2203/45264 ,  H03F2203/45286 ,  H03G1/0023 ,  H03G1/0029 ,  H03G3/3052 ,  H03H7/25 ,  H03H11/04 ,  H03H11/1291 ,  H03H11/53 ,  H03H11/54 ,  H03H19/004 ,  H03J1/0075 ,  H03J3/04 ,  H03J3/08 ,  H03J3/185 ,  H03J2200/10 ,  H03L7/10 ,  H03L7/183 ,  H03L7/23 ,  H03L2207/06 ,  H01L2924/00

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

Abstract translation: 描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。 接收机前端提供可编程衰减和可编程增益低噪声放大器。 频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。 过滤器调谐和电感Q补偿温度在芯片上执行。 滤波器采用多轨螺旋电感。 使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。 结合滤波，频率规划提供了额外的镜像抑制。 片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。 差分晶体振荡器有利地用作频率参考。 差分信号传输有利地用于整个接收机。

公开(公告)号：US06650267B2

公开(公告)日：2003-11-18

申请号：US10146259

申请日：2002-05-15

Applicant: Klaas Bult ,  Aaron W. Buchwald

Inventor： Klaas Bult ,  Aaron W. Buchwald

IPC: H03M112

CPC classification number: H03M1/0646 ,  H03M1/36

Abstract: The output of each cell in an A-D converter on an IC chip is dependent upon the relative values of an input voltage and an individual one of progressive fractions of a reference voltage respectively introduced to the branches in a differential amplifier. To minimize output errors from cell mismatches, first and second sets of averaging impedances, preferably resistors, are respectively connected between the output terminals in the first branches, and the output terminals in the second branches, in successive pairs of cells. The impedances have relatively low values, particularly compared to the impedances of current sources connected to the branch output terminals. First and second resistive strips on the chip may be tapped at progressive positions to respectively define the impedances in the first and second sets.

公开(公告)号：US06573851B2

公开(公告)日：2003-06-03

申请号：US10079814

申请日：2002-02-22

Applicant: Klaas Bult

Inventor： Klaas Bult

IPC: H03M112

CPC classification number: H03F3/70 ,  H03M1/361

Abstract: A system and method for converting an analog input signal to a N-bit digital output signal. The invention comprises generating a plurality of reference voltage signals; pre-amplifying, separately, a difference between each of the plurality of reference voltage signals and an analog input signal using a plurality of cascaded, differential, switched-capacitor circuits to output a plurality of pre-amplified difference signals; and determining a zero-crossing result for each of the plurality of pre-amplified difference signals. Then one of a binary 1 and a binary 0 are assigned to each of the compared, pre-amplified signals. The binary 1's and 0's are encoded as an M-bit encoded signal, which is then decoded to output an N-bit digital output signal, wherein M is less that or equal to N.

Abstract translation: 一种用于将模拟输入信号转换成N位数字输出信号的系统和方法。 本发明包括产生多个参考电压信号; 分别对多个参考电压信号中的每一个和使用多个级联差分开关电容电路的模拟输入信号进行预放大，以输出多个预放大的差分信号; 以及确定所述多个预放大差分信号中的每一个的过零结果。 然后将二进制1和二进制0中的一个分配给每个比较的预放大信号。 二进制1和0被编码为M位编码信号，然后将其解码以输出N位数字输出信号，其中M小于或等于N.

公开(公告)号：US06522279B2

公开(公告)日：2003-02-18

申请号：US10175663

申请日：2002-06-20

Applicant: Klaas Bult ,  Chi-Hung Lin

Inventor： Klaas Bult ,  Chi-Hung Lin

IPC: H03M166

CPC classification number: H03M1/0624 ,  H03M1/0682 ,  H03M1/0872 ,  H03M1/685 ,  H03M1/747

Abstract: Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.

公开(公告)号：US06407692B1

公开(公告)日：2002-06-18

申请号：US09702309

申请日：2000-10-31

Applicant: Klaas Bult ,  Aaron W. Buchwald

Inventor： Klaas Bult ,  Aaron W. Buchwald

IPC: H03M112

CPC classification number: H03M1/0646 ,  H03M1/36

Abstract: The output of each cell in an A-D converter on an IC chip is dependent upon the relative values of an input voltage and an individual one of progressive fractions of a reference voltage respectively introduced to the branches in a differential amplifier. To minimize output errors from cell mismatches, first and second sets of averaging impedances, preferably resistors, are respectively connected between the output terminals in the first branches, and the output terminals in the second branches, in successive pairs of cells. The impedances have relatively low values, particularly compared to the impedances of current sources connected to the branch output terminals. First and second resistive strips on the chip may be tapped at progressive positions to respectively define the impedances in the first and second sets. One end of each strip may be connected to the opposite end of the other strip to define a closed impedance loop for minimizing averaging errors at the strip ends. Different fractions of the reference voltage are associated with each individual impedance in the first and second sets. Such reference voltage fractions have a particular repetitive relationship. In this way, the number of output terminals is reduced and cell mismatches are reduced. The different outputs at each individual impedance are determined for the progressive fractions of the reference voltage at such impedance. Successive voltage fractions for each impedance have opposite polarities to provide a folding relationship. Such outputs may be cascaded to further reduce cell mismatches and the number of output terminals.

Abstract translation: IC芯片上的A-D转换器中的每个单元的输出取决于分别引入差分放大器中的分支的参考电压的输入电压和逐行分数的相对值。 为了使来自单元错配的输出误差最小化，第一和第二组平均阻抗（优选电阻）分别连接在第一分支中的输出端和第二分支中的输出端之间，以连续的单元对。 阻抗具有相对较低的值，特别是与连接到分支输出端子的电流源的阻抗相比较。 芯片上的第一和第二电阻条可以在逐行位置被分接，以分别限定第一和第二组中的阻抗。 每个条带的一端可以连接到另一条带的相对端，以限定用于最小化带端部处的平均误差的闭合阻抗环路。 参考电压的不同分数与第一组和第二组中的每个单独的阻抗相关联。 这种参考电压分数具有特定的重复关系。 以这种方式，减少了输出端子的数量并减小了单元的不匹配。 在这种阻抗下，针对参考电压的渐进分数确定每个单独阻抗的不同输出。 每个阻抗的连续电压分数具有相反的极性以提供折叠关系。 这样的输出可以级联以进一步减少单元错配和输出端子的数量。

公开(公告)号：US5835048A

公开(公告)日：1998-11-10

申请号：US792941

申请日：1997-01-22

Applicant: Klaas Bult

Inventor： Klaas Bult

IPC: H03M1/06 ,  H03M1/36

CPC classification number: H03M1/0646 ,  H03M1/36

Abstract: An analog-to-digital converter (ADC) formed on an integrated circuit chip from a plurality of cells includes a differential amplifier having first and second branches. The branches in each cell respectively have first and second transistors respectively responsive to an input voltage and an individual one of progressive fractions of a reference voltage. The relative outputs from the branches for each cell are dependent upon the relative values of the two voltages introduced to the cell. To minimize cell mismatches and the effects of these mismatches on cell outputs, first and second sets of averaging impedances, preferably resistors, are respectively connected between the output terminals of the first branch transistors, and between the output terminals of the second branch transistors, in successive pairs of cells. Current sources connected to the output terminals of the transistors in the first and second branches have characteristics (preferably impedances approaching infinity) to force the load bearing currents from the transistors to flow through the impedances in the first and second sets. The impedances have relatively low values, particularly in comparison to the impedances of the current sources, to reduce cell mismatches. First and second resistive strips on the chip may be tapped at progressive positions to respectively define the impedances in the first and second sets. One end of each strip may be connected to the opposite end of the other strip to define a closed impedance loop to minimize averaging errors at the ends of the strip.

Abstract translation: 从多个单元形成在集成电路芯片上的模数转换器（ADC）包括具有第一和第二分支的差分放大器。 每个单元中的分支分别具有第一和第二晶体管，其分别响应于参考电压的输入电压和逐行分数的单独一个。 每个单元的分支的相对输出取决于引入单元的两个电压的相对值。 为了最小化单元错配和这些不匹配对单元输出的影响，第一和第二组平均阻抗（优选电阻器）分别连接在第一分支晶体管的输出端之间以及第二分支晶体管的输出端之间， 连续的细胞对。 连接到第一和第二分支中的晶体管的输出端子的电流源具有强制来自晶体管的负载电流流过第一和第二组中的阻抗的特性（优选地是接近无穷大的阻抗）。 阻抗具有相对较低的值，特别是与电流源的阻抗相比，减少电池不匹配。 芯片上的第一和第二电阻条可以在逐行位置被分接，以分别限定第一和第二组中的阻抗。 每个条带的一端可以连接到另一条带的相对端，以限定闭合阻抗环路，以最小化条带端部处的平均误差。

公开(公告)号：US08410820B2

公开(公告)日：2013-04-02

申请号：US13026904

申请日：2011-02-14

Applicant: Klaas Bult ,  Rudy Van de Plassche ,  Jan Mulder

Inventor： Klaas Bult ,  Rudy Van de Plassche ,  Jan Mulder

IPC: G01R19/00 ,  G11C7/00 ,  H03K3/45

CPC classification number: H03K3/356043 ,  H03K3/012 ,  H03K3/35613 ,  H03K3/356182 ,  H03K3/356191 ,  H03M1/002 ,  H03M1/362

Abstract: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit port. This decreases the time in which the latch circuit port receiving the current signal greater than the bias current reaches a steady state voltage.

公开(公告)号：US08195117B2

公开(公告)日：2012-06-05

申请号：US12789928

申请日：2010-05-28

Applicant: Klaas Bult ,  Ramon A. Gomez

Inventor： Klaas Bult ,  Ramon A. Gomez

IPC: H04B1/06 ,  H04K3/00

CPC classification number: H03D3/18 ,  H01F17/0006 ,  H01F17/0013 ,  H01F27/34 ,  H01F27/40 ,  H01F27/42 ,  H01F2017/0053 ,  H01F2021/125 ,  H01L23/5227 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03B5/04 ,  H03B5/364 ,  H03D7/161 ,  H03D7/18 ,  H03F1/26 ,  H03F1/3211 ,  H03F3/195 ,  H03F3/45183 ,  H03F3/45188 ,  H03F3/68 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2200/447 ,  H03F2200/63 ,  H03F2203/45264 ,  H03F2203/45286 ,  H03G1/0023 ,  H03G1/0029 ,  H03G3/3052 ,  H03H7/25 ,  H03H11/04 ,  H03H11/1291 ,  H03H11/53 ,  H03H11/54 ,  H03H19/004 ,  H03J1/0075 ,  H03J3/04 ,  H03J3/08 ,  H03J3/185 ,  H03J2200/10 ,  H03L7/10 ,  H03L7/183 ,  H03L7/23 ,  H03L2207/06 ,  H01L2924/00

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver.

Abstract translation: 描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。 接收机前端提供可编程衰减和可编程增益低噪声放大器。 频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。 过滤器调谐和电感Q补偿温度在芯片上执行。 滤波器采用多轨螺旋电感。 使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。 结合滤波，频率规划提供了额外的镜像抑制。 片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。 差分晶体振荡器有利地用作频率参考。 差分信号传输有利地用于整个接收机。