公开(公告)号：US20090273385A1

公开(公告)日：2009-11-05

申请号：US12347446

申请日：2008-12-31

申请人： Chang-Kyu CHOI ,  Kyung-Hoon Kim

发明人： Chang-Kyu CHOI ,  Kyung-Hoon Kim

IPC分类号： H03L5/00

CPC分类号： H03K5/08 ,  H04L25/0264 ,  H04L25/028

摘要： An output circuit of a semiconductor device includes a signal selector configured to receive first and second input data signals and sequentially outputting the first and second input data signals in response to a phase signal; and an output level controller configured to control a voltage level of an output signal of the signal selector based on the first and second input data signals.

摘要翻译： 半导体器件的输出电路包括：信号选择器，被配置为接收第一和第二输入数据信号，并响应于相位信号顺序地输出第一和第二输入数据信号; 以及输出电平控制器，被配置为基于第一和第二输入数据信号来控制信号选择器的输出信号的电压电平。

公开(公告)号：US20090273381A1

公开(公告)日：2009-11-05

申请号：US12164199

申请日：2008-06-30

申请人： Kyung-Hoon KIM ,  Bo-Kyeom Kim ,  Taek-Sang Song

发明人： Kyung-Hoon KIM ,  Bo-Kyeom Kim ,  Taek-Sang Song

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/07 ,  H03L7/087 ,  H03L7/091 ,  H03L7/093

摘要： A delay locked loop circuit for compensating for a phase skew of a memory device includes a first delay locking unit configured to delay an external clock of the memory device by a first amount of delay to output a first internal clock, a second locking unit configured to delay the external clock by a second amount of delay to output a second internal clock, the second amount of delay being greater than the first amount of delay, and a selecting unit configured to select one of the first internal clock and the second internal clock as an internal clock of the memory device.

摘要翻译： 用于补偿存储器件的相位偏移的延迟锁定环路包括：第一延迟锁定单元，被配置为将存储器件的外部时钟延迟第一延迟量以输出第一内部时钟;第二锁定单元，被配置为 将外部时钟延迟第二延迟量以输出第二内部时钟，第二延迟量大于第一延迟量，以及选择单元，被配置为选择第一内部时钟和第二内部时钟之一作为 存储器件的内部时钟。

公开(公告)号：US07612593B2

公开(公告)日：2009-11-03

申请号：US12005923

申请日：2007-12-28

申请人： Kyung-Hoon Kim ,  Jun-Woo Lee ,  Dae-Kun Yoon ,  Taek-Sang Song

发明人： Kyung-Hoon Kim ,  Jun-Woo Lee ,  Dae-Kun Yoon ,  Taek-Sang Song

IPC分类号： H03K5/02

CPC分类号： H03K5/1534 ,  G11C7/22 ,  G11C7/222 ,  H03K5/1565

摘要： Semiconductor memory device with duty correction circuit includes a clock edge detector configured to generate first and second detection pulses in response to a transition timing of a common clock signal in an initial measurement operation; a duty detector configured to compare the first and second detection pulses to output comparison result signals; and a code counter configured to control the duty detector based on the comparison signals outputted from the duty detector in the initial measurement operation.

摘要翻译： 具有占空比校正电路的半导体存储器件包括：时钟边缘检测器，被配置为响应于在初始测量操作中的公共时钟信号的转变定时产生第一和第二检测脉冲; 负载检测器，被配置为将所述第一和第二检测脉冲与输出比较结果信号进行比较; 以及代码计数器，被配置为基于在初始测量操作中从占空比检测器输出的比较信号来控制占空比检测器。

公开(公告)号：US07551501B2

公开(公告)日：2009-06-23

申请号：US11647409

申请日：2006-12-29

申请人： Kyung-Hoon Kim ,  Patrick B. Moran

发明人： Kyung-Hoon Kim ,  Patrick B. Moran

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G01K13/00 ,  G11C5/143 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/20 ,  G11C11/406 ,  G11C11/40626 ,  G11C2029/5002 ,  G11C2211/4061

摘要： A semiconductor memory device includes a thermosensor that senses present temperatures of the device and confirms whether the temperature values are valid. The thermosensor includes a temperature sensing unit, a storage unit and an initializing unit. The temperature sensing unit senses temperatures in response to a driving signal. The storage unit stores output signals of the temperature sensing unit and outputs temperature values. The initializing unit initializes the storage unit after a predetermined time from an activation of the driving signal. A driving method includes driving the thermosensor in response to the driving signal, requesting a re-driving after a predetermined time from the activation of the driving signal, and re-driving the thermosensor in response to the driving signal input again.

摘要翻译： 半导体存储器件包括感测器件的当前温度并确认温度值是否有效的热敏传感器。 热敏传感器包括温度检测单元，存储单元和初始化单元。 温度感测单元响应于驱动信号感测温度。 存储单元存储温度感测单元的输出信号并输出​​温度值。 初始化单元在从驱动信号的激活开始的预定时间之后初始化存储单元。 驱动方法包括响应于驱动信号驱动热敏传感器，在从驱动信号的激活开始的预定时间之后请求重新驱动，并且响应于再次输入驱动信号重新驱动热敏传感器。

公开(公告)号：US20090146684A1

公开(公告)日：2009-06-11

申请号：US12364656

申请日：2009-02-03

申请人： Kyung Hoon KIM

发明人： Kyung Hoon KIM

IPC分类号： H03K19/003 ,  H03K19/0175

CPC分类号： G11C8/08 ,  G11C7/02 ,  G11C7/08 ,  G11C7/12 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4094 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50008 ,  G11C2029/1202 ,  G11C2211/4065

摘要： A circuit for controlling a driver of a semiconductor memory apparatus includes a driving unit having an impedance that is set according to a code value; a driving reinforcing control unit configured to output an adjustment code for a predetermined time; and a driving reinforcing unit configured to output a reinforcing code obtained by adjusting the code value using the adjustment code, wherein the reinforcing code reinforce a driving capability of the driving unit.

摘要翻译： 用于控制半导体存储装置的驱动器的电路包括：具有根据代码值设置的阻抗的驱动单元; 驱动加强控制单元，被配置为输出预定时间的调整代码; 以及驱动加强单元，其被配置为输出通过使用所述调整代码调整所述代码值而获得的加强代码，其中所述加强代码加强所述驱动单元的驱动能力。

公开(公告)号：US07541831B2

公开(公告)日：2009-06-02

申请号：US11987937

申请日：2007-12-06

申请人： Kyung-Hoon Kim

发明人： Kyung-Hoon Kim

IPC分类号： H03K17/16

CPC分类号： H04L25/0278 ,  G01R31/31715 ,  G11C29/02 ,  G11C29/022 ,  G11C29/50008 ,  G11C2207/2254

摘要： A semiconductor memory device includes a reference signal generating unit for generating a reference signal; a comparing unit for comparing the reference signal with a test signal applied to a test pad to output an adjusted value after adjusting the adjusted value until the test signal is equal to the reference signal; an impedance measuring unit for measuring an impedance of the test pad based on the adjusted value to output the test signal; an impedance adjusting unit for adjusting an impedance of a data I/O pad to have an impedance value corresponding to the adjusted value outputted when the test signal is equal to the reference signal; an impedance control unit for controlling the comparing unit so that the adjusted value is outputted when the test signal is equal to the reference signal; and a reference signal control unit for adjusting a voltage level of the reference signal.

摘要翻译： 半导体存储器件包括用于产生参考信号的参考信号产生单元; 比较单元，用于将参考信号与施加到测试垫的测试信号进行比较，以在调整了调整值直到测试信号等于参考信号之后输出调整值; 阻抗测量单元，用于基于所述调整值来测量所述测试垫的阻抗以输出所述测试信号; 阻抗调整单元，用于调整数据I / O焊盘的阻抗，使阻抗值对应于当测试信号等于参考信号时输出的调整值; 阻抗控制单元，用于控制比较单元，使得当测试信号等于参考信号时，输出调整值; 以及用于调整参考信号的电压电平的参考信号控制单元。

公开(公告)号：US20090121701A1

公开(公告)日：2009-05-14

申请号：US12266693

申请日：2008-11-07

申请人： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

发明人： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

IPC分类号： G05F3/16

CPC分类号： G05F3/30 ,  G11C5/147

摘要： A bandgap reference generating circuit includes an operational amplifier configured to generate a bandgap reference voltage; and a gain controller configured to control a gain of the operational amplifier with different values in a normal mode and a low power mode.

摘要翻译： 带隙参考产生电路包括：运算放大器，被配置为产生带隙参考电压; 以及增益控制器，被配置为在正常模式和低功率模式下以不同的值来控制运算放大器的增益。

公开(公告)号：US20090115485A1

公开(公告)日：2009-05-07

申请号：US12157287

申请日：2008-06-09

申请人： Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

发明人： Kyung-Hoon Kim ,  Sang-Yeon Byeon ,  Chang-Kyu Choi

IPC分类号： H03H11/26

CPC分类号： H03H11/26

摘要： Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units.

摘要翻译： 用于恢复高度集成的半导体存储装置中的时钟数据的电路和方法包括：多个信号接收单元，被配置为通过多个输入/输出焊盘接收信号，并根据接收的参考时钟传送信号，信号接收单元被分成 多个相位检测单元，被配置为检测从信号接收单元的组输出的信号的相位;多个相位检测控制单元，被配置为控制相位检测单元，使得相位检测单元顺序地检测相位检测单元的相位; 从信号接收单元的每个组输出的信号和被配置为输出从相位检测单元输出的信号的通知单元。

公开(公告)号：US20090115450A1

公开(公告)日：2009-05-07

申请号：US12215830

申请日：2008-06-30

申请人： Kyung-Whan Kim ,  Kyung-Hoon Kim

发明人： Kyung-Whan Kim ,  Kyung-Hoon Kim

IPC分类号： H03K19/003 ,  H03K19/00

CPC分类号： G11C5/063 ,  G11C7/1051 ,  G11C7/1057 ,  G11C2207/2254

摘要： A termination impedance control circuit is capable of controlling a dynamic ODT operation in a DDR3-level semiconductor memory device. The termination impedance control circuit includes a counter unit configured to count an external clock and an internal clock to output a first code and a second code, respectively, and a dynamic controller configured to enable a dynamic termination operation by comparing the first code with the second code in response to a write command and disable the dynamic termination operation after a predetermined time, determined according to a burst length, has lapsed after the dynamic termination operation is enabled.

摘要翻译： 终端阻抗控制电路能够控制DDR3级半导体存储器件中的动态ODT操作。 终端阻抗控制电路包括：计数器单元，被配置为对外部时钟和内部时钟进行计数，以分别输出第一代码和第二代码;以及动态控制器，被配置为通过将第一代码与第二代码进行比较来实现动态终止操作 响应于写命令的代码，并且在启用了动态终止操作之后已经经过了在根据突发长度确定的预定时间之后禁用动态终止操作。

公开(公告)号：US20090058464A1

公开(公告)日：2009-03-05

申请号：US12005443

申请日：2007-12-26

申请人： Kyung-Hoon Kim ,  Dae-Han Kwon

发明人： Kyung-Hoon Kim ,  Dae-Han Kwon

IPC分类号： H03K19/0175 ,  H03K19/094

CPC分类号： H03K19/018521 ,  H03K19/0948

摘要： A current mode logic (CML)-complementary metal oxide semiconductor (CMOS) converter prevents change of a duty ratio to stably operate during an operation for converting a CML level signal into a CMOS level signal. The CML-CMOS converter includes a reference level shifting unit configured to receive a CML signal swinging about a first reference level to shift a swing reference level to a second reference level; and an amplifying unit configured to amplify an output signal of the reference level shifting unit to output the amplified signal as a CMOS signal.

摘要翻译： 电流模式逻辑（CML） - 互补金属氧化物半导体（CMOS）转换器在用于将CML电平信号转换为CMOS电平信号的操作期间防止占空比的变化以稳定地操作。 CML-CMOS转换器包括参考电平移位单元，被配置为接收围绕第一参考电平摆动的CML信号，以将摆幅参考电平移位到第二参考电平; 以及放大单元，被配置为放大参考电平移位单元的输出信号以输出放大的信号作为CMOS信号。