公开(公告)号：US20080122086A1

公开(公告)日：2008-05-29

申请号：US11592220

申请日：2006-11-03

Applicant: Pei-Haw Tsao ,  Bill Kiang ,  Pao-Kang Niu ,  Liang-Chen Lin ,  I-Tai Liu

Inventor： Pei-Haw Tsao ,  Bill Kiang ,  Pao-Kang Niu ,  Liang-Chen Lin ,  I-Tai Liu

IPC: H01L23/488 ,  H01L21/44

CPC classification number: H01L24/10 ,  H01L23/3192 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Solder bump structures for semiconductor device packaging is provided. In one embodiment, a semiconductor device comprises a substrate having a bond pad and a first passivation layer formed thereabove, the first passivation layer having an opening therein exposing a portion of the bond pad. A metal pad layer is formed on a portion of the bond pad, wherein the metal pad layer contacts the bond pad. A second passivation layer is formed above the metal pad layer, the second passivation layer having an opening therein exposing a portion of the metal pad layer. A patterned and etched polyimide layer is formed on a portion of the metal pad layer and a portion of the second passivation layer. A conductive layer is formed above a portion of the etched polyimide layer and a portion of the metal pad layer, wherein the conductive layer contacts the metal pad layer. A conductive bump structure is connected to the conductive layer.

Abstract translation: 提供了用于半导体器件封装的焊接凸块结构。 在一个实施例中，半导体器件包括具有接合焊盘和在其上形成的第一钝化层的衬底，其中第一钝化层具有暴露焊接焊盘的一部分的开口。 在接合焊盘的一部分上形成金属焊盘层，其中金属焊盘层与接合焊盘接触。 第二钝化层形成在金属焊盘层的上方，第二钝化层在其中具有露出金属焊盘层的一部分的开口。 图案化和蚀刻的聚酰亚胺层形成在金属焊盘层的一部分和第二钝化层的一部分上。 在蚀刻的聚酰亚胺层的一部分和金属焊盘层的一部分上形成导电层，其中导电层与金属焊盘层接触。 导电凸块结构连接到导电层。

公开(公告)号：US20090121222A1

公开(公告)日：2009-05-14

申请号：US12354338

申请日：2009-01-15

Applicant: Ta-Chih Peng ,  Yu-Ting Lin ,  Liang-Chen Lin ,  Ko-Yi Lee

Inventor： Ta-Chih Peng ,  Yu-Ting Lin ,  Liang-Chen Lin ,  Ko-Yi Lee

IPC: H01L23/488

CPC classification number: H01L24/05 ,  H01L22/34 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A test structure to detect vertical leakage in a multi-layer flip chip pad stack or similar semiconductor device. The test structure is integrated into the semiconductor device when it is fabricated. A metal layer includes at least two portions that are electrically isolated from each other; one portion being disposed under a test pad, and another portion being disposed under a pad associated with a pad structure being tested. The metal layer in most cases is separated from a top metal layer directly underlying the pads by an inter-metal dielectric (IMD) layer. A metal layer portion underlying the pad to be tested forms a recess in which a conductive member is disposed without making electrical contact. The conductive line is electrically coupled to a test portion of the same or, alternately, of a different metal layer. The test structure may be implemented on multiple layers, with recesses portions underlying the same or different pads.

Abstract translation: 用于检测多层倒装芯片堆栈或类似半导体器件中的垂直泄漏的测试结构。 测试结构在制造时被集成到半导体器件中。 金属层包括彼此电隔离的至少两个部分; 一部分设置在测试垫下方，另一部分设置在与被测试的垫结构相关联的垫下方。 大多数情况下，金属层通过金属间电介质（IMD）层与直接位于焊盘下方的顶部金属层分离。 待测试垫下面的金属层部分形成凹部，其中布置导电部件而不进行电接触。 导电线电耦合到相同或交替地不同金属层的测试部分。 测试结构可以在多个层上实现，其中凹陷部分位于相同或不同的垫下。

公开(公告)号：US20080083992A1

公开(公告)日：2008-04-10

申请号：US11539498

申请日：2006-10-06

Applicant: Liang-Chen Lin ,  Pei-Haw Tsao

Inventor： Liang-Chen Lin ,  Pei-Haw Tsao

IPC: H01L21/44 ,  H01L23/485

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05006 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/45124 ,  H01L2224/48463 ,  H01L2224/48747 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A pad structure includes a first metal-containing layer formed over a substrate. A first passivation layer is formed over the first metal-containing layer. The first passivation layer has a first opening partially exposing the first metal-containing layer. A pad layer is formed over the first passivation layer, covering the first opening. The pad layer includes a probing region configured to be contacted by a probe and a bonding region configured to have a wired bonded to it. The probing region contacts the first metal-containing layer through the first opening, and the bonding region overlies a portion of the first passivation layer.

Abstract translation: 衬垫结构包括在衬底上形成的第一含金属层。 在第一含金属层上形成第一钝化层。 第一钝化层具有部分暴露第一含金属层的第一开口。 衬垫层形成在第一钝化层上，覆盖第一开口。 衬垫层包括构造成由探针接触的探测区域和被配置为与其接合的接合区域。 探测区域通过第一开口接触第一含金属层，并且接合区域覆盖第一钝化层的一部分。