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1.发明申请System-in-package packaging for minimizing bond wire contamination and yield loss 有权系统级封装封装，最大限度地减少接合线污染和产量损失公开(公告)号：US20080169557A1
公开(公告)日：2008-07-17
申请号：US11652086
申请日：2007-01-11
申请人： Pei-Haw Tsao , Bill Kiang , Liang-Chen Lin , Pao-Kang Niu , I-Tai Liu
发明人： Pei-Haw Tsao , Bill Kiang , Liang-Chen Lin , Pao-Kang Niu , I-Tai Liu
IPC分类号： H01L23/34
CPC分类号： H01L25/0657 , H01L21/563 , H01L23/3128 , H01L24/28 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L2224/16225 , H01L2224/29101 , H01L2224/2919 , H01L2224/2929 , H01L2224/29298 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/48475 , H01L2224/4848 , H01L2224/48499 , H01L2224/48599 , H01L2224/48699 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2224/8385 , H01L2224/85051 , H01L2225/0651 , H01L2225/06517 , H01L2225/06527 , H01L2225/06562 , H01L2225/06582 , H01L2924/00011 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2224/78 , H01L2924/00 , H01L2924/00012 , H01L2924/3512 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/0401 , H01L2224/85399 , H01L2224/05599
摘要： A system-in-package (SiP) package is provided. In one embodiment, the SiP package comprises a substrate having a first surface and a second surface opposite the first surface, the substrate having a set of bond wire studs on bond pads formed on the second surface thereof; a first semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the first semiconductor chip is mounted to the second surface of the substrate by means of solder bumps; an underfill material disposed between the first semiconductor chip and the substrate, encapsulating the solder bumps; a second semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the second semiconductor chip is mounted to the second surface of the first semiconductor chip; and a set of bond wires electrically coupled from the second semiconductor chip to the set of bond wire studs on the substrate.
摘要翻译： 提供系统级封装（SiP）封装。 在一个实施例中，SiP封装包括具有第一表面和与第一表面相对的第二表面的衬底，衬底在其第二表面上形成的接合焊盘上具有一组接合线柱; 第一半导体芯片，具有与第一表面相对的第一表面和第二表面，其中第一半导体芯片的第一表面通过焊料凸块安装到基板的第二表面; 设置在所述第一半导体芯片和所述基板之间的底部填充材料，封装所述焊料凸块; 第二半导体芯片，具有与第一表面相对的第一表面和第二表面，其中第二半导体芯片的第一表面安装到第一半导体芯片的第二表面; 以及从第二半导体芯片电耦合到衬底上的一组接合线柱的一组接合线。
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公开(公告)号：US20080122100A1
公开(公告)日：2008-05-29
申请号：US11557372
申请日：2006-11-07
申请人： Pei-Haw Tsao , Liang-Chen Lin , Pao-Kang Niu , I-Tai Liu , Bill Kiang
发明人： Pei-Haw Tsao , Liang-Chen Lin , Pao-Kang Niu , I-Tai Liu , Bill Kiang
IPC分类号： H01L23/488 , H01L21/4763
CPC分类号： H01L24/05 , H01L24/03 , H01L2224/02166 , H01L2224/05093 , H01L2224/05094 , H01L2224/05554 , H01L2224/05556 , H01L2224/056 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/14
摘要： An improved via arrangement for a bonding pad structure is disclosed comprising an array of vias surrounded by a line via. The line via provides a barrier to cracks in the dielectric layer encompassing the via array. Although cracks are able to spread relatively unhindered between the vias of the via array, they are blocked by the line via and thus can not spread to neighboring regions of the chip or wafer. The line via can be provided in a variety of shapes and dimensions, to suit a desired application. Additionally, due to its substantially uninterrupted length, the line via provides added strength to the bond pad.
摘要翻译： 公开了一种用于焊盘结构的改进的通孔布置，其包括由线路通孔包围的通孔阵列。 线路通孔提供对包围通孔阵列的介电层中的裂纹的屏障。 虽然裂纹能够在通孔阵列的通孔之间相对不受阻碍地扩散，但是它们被线通孔阻挡，因此不能扩散到芯片或晶片的相邻区域。 线路通孔可以以各种形状和尺寸提供，以适应期望的应用。 另外，由于其基本上不间断的长度，线路通孔为接合焊盘提供附加的强度。
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公开(公告)号：US20080122086A1
公开(公告)日：2008-05-29
申请号：US11592220
申请日：2006-11-03
申请人： Pei-Haw Tsao , Bill Kiang , Pao-Kang Niu , Liang-Chen Lin , I-Tai Liu
发明人： Pei-Haw Tsao , Bill Kiang , Pao-Kang Niu , Liang-Chen Lin , I-Tai Liu
IPC分类号： H01L23/488 , H01L21/44
CPC分类号： H01L24/10 , H01L23/3192 , H01L24/13 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05572 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2224/05552 , H01L2924/00
摘要： Solder bump structures for semiconductor device packaging is provided. In one embodiment, a semiconductor device comprises a substrate having a bond pad and a first passivation layer formed thereabove, the first passivation layer having an opening therein exposing a portion of the bond pad. A metal pad layer is formed on a portion of the bond pad, wherein the metal pad layer contacts the bond pad. A second passivation layer is formed above the metal pad layer, the second passivation layer having an opening therein exposing a portion of the metal pad layer. A patterned and etched polyimide layer is formed on a portion of the metal pad layer and a portion of the second passivation layer. A conductive layer is formed above a portion of the etched polyimide layer and a portion of the metal pad layer, wherein the conductive layer contacts the metal pad layer. A conductive bump structure is connected to the conductive layer.
摘要翻译： 提供了用于半导体器件封装的焊接凸块结构。 在一个实施例中，半导体器件包括具有接合焊盘和在其上形成的第一钝化层的衬底，其中第一钝化层具有暴露焊接焊盘的一部分的开口。 在接合焊盘的一部分上形成金属焊盘层，其中金属焊盘层与接合焊盘接触。 第二钝化层形成在金属焊盘层的上方，第二钝化层在其中具有露出金属焊盘层的一部分的开口。 图案化和蚀刻的聚酰亚胺层形成在金属焊盘层的一部分和第二钝化层的一部分上。 在蚀刻的聚酰亚胺层的一部分和金属焊盘层的一部分上形成导电层，其中导电层与金属焊盘层接触。 导电凸块结构连接到导电层。
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4.发明授权System-in-package packaging for minimizing bond wire contamination and yield loss 有权系统级封装封装，最大限度地减少接合线污染和产量损失公开(公告)号：US08217520B2
公开(公告)日：2012-07-10
申请号：US12723433
申请日：2010-03-12
申请人： Pei-Haw Tsao , Bill Kiang , Liang-Chen Lin , Pao-Kang Niu , I-Tai Liu
发明人： Pei-Haw Tsao , Bill Kiang , Liang-Chen Lin , Pao-Kang Niu , I-Tai Liu
CPC分类号： H01L25/0657 , H01L21/563 , H01L23/3128 , H01L24/28 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L2224/16225 , H01L2224/29101 , H01L2224/2919 , H01L2224/2929 , H01L2224/29298 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/48475 , H01L2224/4848 , H01L2224/48499 , H01L2224/48599 , H01L2224/48699 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2224/8385 , H01L2224/85051 , H01L2225/0651 , H01L2225/06517 , H01L2225/06527 , H01L2225/06562 , H01L2225/06582 , H01L2924/00011 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2224/78 , H01L2924/00 , H01L2924/00012 , H01L2924/3512 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/0401 , H01L2224/85399 , H01L2224/05599
摘要： A system-in-package (SiP) package is provided. In one embodiment, the SiP package comprises a substrate having a first surface and a second surface opposite the first surface, the substrate having a set of bond wire studs on bond pads formed on the second surface thereof; a first semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the first semiconductor chip is mounted to the second surface of the substrate by means of solder bumps; an underfill material disposed between the first semiconductor chip and the substrate, encapsulating the solder bumps; a second semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the second semiconductor chip is mounted to the second surface of the first semiconductor chip; and a set of bond wires electrically coupled from the second semiconductor chip to the set of bond wire studs on the substrate.
摘要翻译： 提供系统级封装（SiP）封装。 在一个实施例中，SiP封装包括具有第一表面和与第一表面相对的第二表面的衬底，衬底在其第二表面上形成的接合焊盘上具有一组接合线柱; 第一半导体芯片，具有与第一表面相对的第一表面和第二表面，其中第一半导体芯片的第一表面通过焊料凸块安装到基板的第二表面; 设置在所述第一半导体芯片和所述衬底之间，包覆该焊料凸块的底部填充材料; 具有第一表面和第一表面，其中所述第二半导体芯片的所述第一表面被安装到第一半导体芯片的所述第二表面相对的第二表面的第二半导体芯片; 和一组键合引线的电从第二半导体芯片的基板上所设置的接合线螺柱连接。
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5.发明授权System-in-package packaging for minimizing bond wire contamination and yield loss 有权系统级封装封装，最大限度地减少接合线污染和产量损失公开(公告)号：US07719122B2
公开(公告)日：2010-05-18
申请号：US11652086
申请日：2007-01-11
申请人： Pei-Haw Tsao , Bill Kiang , Liang-Chen Lin , Pao-Kang Niu , I-Tai Liu
发明人： Pei-Haw Tsao , Bill Kiang , Liang-Chen Lin , Pao-Kang Niu , I-Tai Liu
CPC分类号： H01L25/0657 , H01L21/563 , H01L23/3128 , H01L24/28 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L2224/16225 , H01L2224/29101 , H01L2224/2919 , H01L2224/2929 , H01L2224/29298 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/48475 , H01L2224/4848 , H01L2224/48499 , H01L2224/48599 , H01L2224/48699 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2224/8385 , H01L2224/85051 , H01L2225/0651 , H01L2225/06517 , H01L2225/06527 , H01L2225/06562 , H01L2225/06582 , H01L2924/00011 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2224/78 , H01L2924/00 , H01L2924/00012 , H01L2924/3512 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/0401 , H01L2224/85399 , H01L2224/05599
摘要： A system-in-package (SiP) package is provided. In one embodiment, the SiP package comprises a substrate having a first surface and a second surface opposite the first surface, the substrate having a set of bond wire studs on bond pads formed on the second surface thereof; a first semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the first semiconductor chip is mounted to the second surface of the substrate by means of solder bumps; an underfill material disposed between the first semiconductor chip and the substrate, encapsulating the solder bumps; a second semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the second semiconductor chip is mounted to the second surface of the first semiconductor chip; and a set of bond wires electrically coupled from the second semiconductor chip to the set of bond wire studs on the substrate.
摘要翻译： 提供系统级封装（SiP）封装。 在一个实施例中，SiP封装包括具有第一表面和与第一表面相对的第二表面的衬底，衬底在其第二表面上形成的接合焊盘上具有一组接合线柱; 第一半导体芯片，具有与第一表面相对的第一表面和第二表面，其中第一半导体芯片的第一表面通过焊料凸块安装到基板的第二表面; 设置在所述第一半导体芯片和所述基板之间的底部填充材料，封装所述焊料凸块; 第二半导体芯片，具有与第一表面相对的第一表面和第二表面，其中第二半导体芯片的第一表面安装到第一半导体芯片的第二表面; 以及从第二半导体芯片电耦合到衬底上的一组接合线柱的一组接合线。
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6.发明申请SYSTEM-IN-PACKAGE PACKAGING FOR MINIMIZING BOND WIRE CONTAMINATION AND YIELD LOSS 有权用于最小化线束污染和损伤损失的系统级封装公开(公告)号：US20100164091A1
公开(公告)日：2010-07-01
申请号：US12723433
申请日：2010-03-12
申请人： Pei-Haw Tsao , Bill Kiang , Liang-Chen Lin , Pao-Kang Niu , I-Tai Liu
发明人： Pei-Haw Tsao , Bill Kiang , Liang-Chen Lin , Pao-Kang Niu , I-Tai Liu
IPC分类号： H01L25/065 , H01L21/56
CPC分类号： H01L25/0657 , H01L21/563 , H01L23/3128 , H01L24/28 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L2224/16225 , H01L2224/29101 , H01L2224/2919 , H01L2224/2929 , H01L2224/29298 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/48475 , H01L2224/4848 , H01L2224/48499 , H01L2224/48599 , H01L2224/48699 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2224/8385 , H01L2224/85051 , H01L2225/0651 , H01L2225/06517 , H01L2225/06527 , H01L2225/06562 , H01L2225/06582 , H01L2924/00011 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2224/78 , H01L2924/00 , H01L2924/00012 , H01L2924/3512 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/0401 , H01L2224/85399 , H01L2224/05599
摘要： A system-in-package (SiP) package is provided. In one embodiment, the SiP package comprises a substrate having a first surface and a second surface opposite the first surface, the substrate having a set of bond wire studs on bond pads formed on the second surface thereof; a first semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the first semiconductor chip is mounted to the second surface of the substrate by means of solder bumps; an underfill material disposed between the first semiconductor chip and the substrate, encapsulating the solder bumps; a second semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the second semiconductor chip is mounted to the second surface of the first semiconductor chip; and a set of bond wires electrically coupled from the second semiconductor chip to the set of bond wire studs on the substrate.
摘要翻译： 提供系统级封装（SiP）封装。 在一个实施例中，SiP封装包括具有第一表面和与第一表面相对的第二表面的衬底，衬底在其第二表面上形成的接合焊盘上具有一组接合线柱; 第一半导体芯片，具有与第一表面相对的第一表面和第二表面，其中第一半导体芯片的第一表面通过焊料凸块安装到基板的第二表面; 设置在所述第一半导体芯片和所述基板之间的底部填充材料，封装所述焊料凸块; 第二半导体芯片，具有与第一表面相对的第一表面和第二表面，其中第二半导体芯片的第一表面安装到第一半导体芯片的第二表面; 以及从第二半导体芯片电耦合到衬底上的一组接合线柱的一组接合线。
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公开(公告)号：US07679180B2
公开(公告)日：2010-03-16
申请号：US11557372
申请日：2006-11-07
申请人： Pei-Haw Tsao , Liang-Chen Lin , Pao-Kang Niu , I-Tai Liu , Bill Kiang
发明人： Pei-Haw Tsao , Liang-Chen Lin , Pao-Kang Niu , I-Tai Liu , Bill Kiang
CPC分类号： H01L24/05 , H01L24/03 , H01L2224/02166 , H01L2224/05093 , H01L2224/05094 , H01L2224/05554 , H01L2224/05556 , H01L2224/056 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/14
摘要： An improved via arrangement for a bonding pad structure is disclosed comprising an array of vias surrounded by a line via. The line via provides a barrier to cracks in the dielectric layer encompassing the via array. Although cracks are able to spread relatively unhindered between the vias of the via array, they are blocked by the line via and thus can not spread to neighboring regions of the chip or wafer. The line via can be provided in a variety of shapes and dimensions, to suit a desired application. Additionally, due to its substantially uninterrupted length, the line via provides added strength to the bond pad.
摘要翻译： 公开了一种用于焊盘结构的改进的通孔布置，其包括由线路通孔包围的通孔阵列。 线路通孔提供对包围通孔阵列的介电层中的裂纹的屏障。 虽然裂纹能够在通孔阵列的通孔之间相对不受阻碍地扩散，但是它们被线通孔阻挡，因此不能扩散到芯片或晶片的相邻区域。 线路通孔可以以各种形状和尺寸提供，以适应期望的应用。 另外，由于其基本上不间断的长度，线路通孔为接合焊盘提供附加的强度。
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公开(公告)号：US07659632B2
公开(公告)日：2010-02-09
申请号：US11592220
申请日：2006-11-03
申请人： Pei-Haw Tsao , Bill Kiang , Pao-Kang Niu , Liang-Chen Lin , I-Tai Liu
发明人： Pei-Haw Tsao , Bill Kiang , Pao-Kang Niu , Liang-Chen Lin , I-Tai Liu
CPC分类号： H01L24/10 , H01L23/3192 , H01L24/13 , H01L2224/0401 , H01L2224/05124 , H01L2224/05147 , H01L2224/05572 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2224/05552 , H01L2924/00
摘要： Solder bump structures for semiconductor device packaging is provided. In one embodiment, a semiconductor device comprises a substrate having a bond pad and a first passivation layer formed thereabove, the first passivation layer having an opening therein exposing a portion of the bond pad. A metal pad layer is formed on a portion of the bond pad, wherein the metal pad layer contacts the bond pad. A second passivation layer is formed above the metal pad layer, the second passivation layer having an opening therein exposing a portion of the metal pad layer. A patterned and etched polyimide layer is formed on a portion of the metal pad layer and a portion of the second passivation layer. A conductive layer is formed above a portion of the etched polyimide layer and a portion of the metal pad layer, wherein the conductive layer contacts the metal pad layer. A conductive bump structure is connected to the conductive layer.
摘要翻译： 提供了用于半导体器件封装的焊接凸块结构。 在一个实施例中，半导体器件包括具有接合焊盘和在其上形成的第一钝化层的衬底，其中第一钝化层具有暴露焊接焊盘的一部分的开口。 在接合焊盘的一部分上形成金属焊盘层，其中金属焊盘层与接合焊盘接触。 第二钝化层形成在金属焊盘层的上方，第二钝化层在其中具有露出金属焊盘层的一部分的开口。 图案化和蚀刻的聚酰亚胺层形成在金属焊盘层的一部分和第二钝化层的一部分上。 在蚀刻的聚酰亚胺层的一部分和金属焊盘层的一部分上形成导电层，其中导电层与金属焊盘层接触。 导电凸块结构连接到导电层。
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