公开(公告)号：US08441127B2

公开(公告)日：2013-05-14

申请号：US13172470

申请日：2011-06-29

Applicant: Fu-Tsai Hou ,  Liang-Chen Lin

Inventor： Fu-Tsai Hou ,  Liang-Chen Lin

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/16237 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: A device includes a package component, and a metal trace on a surface of the package component. A first and a second dielectric mask cover a top surface and sidewalls of the metal trace, wherein a landing portion of the metal trace is located between the first and the second dielectric masks. The landing portion includes a first portion having a first width, and a second portion connected to an end of the first portion. The second portion has a second width greater than the first width, wherein the first and the second widths are measured in a direction perpendicular to a lengthwise direction of the metal trace.

Abstract translation: 一种装置包括封装部件和在封装部件的表面上的金属迹线。 第一和第二介电掩模覆盖金属迹线的顶表面和侧壁，其中金属迹线的着陆部分位于第一和第二介电掩模之间。 着陆部分包括具有第一宽度的第一部分和连接到第一部分的端部的第二部分。 第二部分具有大于第一宽度的第二宽度，其中在垂直于金属迹线的长度方向的方向上测量第一宽度和第二宽度。

公开(公告)号：US20130001769A1

公开(公告)日：2013-01-03

申请号：US13172470

申请日：2011-06-29

Applicant: Fu-Tsai Hou ,  Liang-Chen Lin

Inventor： Fu-Tsai Hou ,  Liang-Chen Lin

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/16237 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: A device includes a package component, and a metal trace on a surface of the package component. A first and a second dielectric mask cover a top surface and sidewalls of the metal trace, wherein a landing portion of the metal trace is located between the first and the second dielectric masks. The landing portion includes a first portion having a first width, and a second portion connected to an end of the first portion. The second portion has a second width greater than the first width, wherein the first and the second widths are measured in a direction perpendicular to a lengthwise direction of the metal trace.

Abstract translation: 一种装置包括封装部件和在封装部件的表面上的金属迹线。 第一和第二介电掩模覆盖金属迹线的顶表面和侧壁，其中金属迹线的着陆部分位于第一和第二介电掩模之间。 着陆部分包括具有第一宽度的第一部分和连接到第一部分的端部的第二部分。 第二部分具有大于第一宽度的第二宽度，其中在垂直于金属迹线的长度方向的方向上测量第一宽度和第二宽度。

公开(公告)号：US07843058B2

公开(公告)日：2010-11-30

申请号：US11928971

申请日：2007-10-30

Applicant: Pei-Haw Tsao ,  Liang-Chen Lin ,  Pao-Kang Niu

Inventor： Pei-Haw Tsao ,  Liang-Chen Lin ,  Pao-Kang Niu

IPC: H01L23/34

CPC classification number: H01L23/4006 ,  H01L23/42 ,  H01L23/433 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A package structure includes a substrate; a die over and flip bonded on the substrate; a heat sink over the die; and one or more spacer separating the heat sink from the substrate.

Abstract translation: 封装结构包括基板; 在基板上切割并翻转接合; 模具上的散热片; 以及将散热器与衬底分隔开的一个或多个间隔件。

公开(公告)号：US07498680B2

公开(公告)日：2009-03-03

申请号：US11634588

申请日：2006-12-06

Applicant: Ta-Chih Peng ,  Yu-ting Lin ,  Liang-Chen Lin ,  Ko-Yi Lee

Inventor： Ta-Chih Peng ,  Yu-ting Lin ,  Liang-Chen Lin ,  Ko-Yi Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/05 ,  H01L22/34 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A test structure to detect vertical leakage in a multi-layer flip chip pad stack or similar semiconductor device. The test structure is integrated into the semiconductor device when it is fabricated. A metal layer includes at least two portions that are electrically isolated from each other; one portion being disposed under a test pad, and another portion being disposed under a pad associated with a pad structure being tested. The metal layer in most cases is separated from a top metal layer directly underlying the pads by an inter-metal dielectric (IMD) layer. A metal layer portion underlying the pad to be tested forms a recess in which a conductive member is disposed without making electrical contact. The conductive line is electrically coupled to a test portion of the same or, alternately, of a different metal layer. The test structure may be implemented on multiple layers, with recesses portions underlying the same or different pads.

Abstract translation: 用于检测多层倒装芯片堆栈或类似半导体器件中的垂直泄漏的测试结构。 测试结构在制造时被集成到半导体器件中。 金属层包括彼此电隔离的至少两个部分; 一部分设置在测试垫下方，另一部分设置在与待测试的垫结构相关联的垫下方。 大多数情况下，金属层通过金属间电介质（IMD）层与直接位于焊盘下方的顶部金属层分离。 待测试垫下面的金属层部分形成凹部，其中布置导电部件而不进行电接触。 导电线电耦合到相同或交替地不同金属层的测试部分。 测试结构可以在多层上实现，其中凹部位于相同或不同的垫下。

公开(公告)号：US20080169557A1

公开(公告)日：2008-07-17

申请号：US11652086

申请日：2007-01-11

Applicant: Pei-Haw Tsao ,  Bill Kiang ,  Liang-Chen Lin ,  Pao-Kang Niu ,  I-Tai Liu

Inventor： Pei-Haw Tsao ,  Bill Kiang ,  Liang-Chen Lin ,  Pao-Kang Niu ,  I-Tai Liu

IPC: H01L23/34

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/3128 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/16225 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29298 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48475 ,  H01L2224/4848 ,  H01L2224/48499 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/85051 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/0401 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A system-in-package (SiP) package is provided. In one embodiment, the SiP package comprises a substrate having a first surface and a second surface opposite the first surface, the substrate having a set of bond wire studs on bond pads formed on the second surface thereof; a first semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the first semiconductor chip is mounted to the second surface of the substrate by means of solder bumps; an underfill material disposed between the first semiconductor chip and the substrate, encapsulating the solder bumps; a second semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the second semiconductor chip is mounted to the second surface of the first semiconductor chip; and a set of bond wires electrically coupled from the second semiconductor chip to the set of bond wire studs on the substrate.

Abstract translation: 提供系统级封装（SiP）封装。 在一个实施例中，SiP封装包括具有第一表面和与第一表面相对的第二表面的衬底，衬底在其第二表面上形成的接合焊盘上具有一组接合线柱; 第一半导体芯片，具有与第一表面相对的第一表面和第二表面，其中第一半导体芯片的第一表面通过焊料凸块安装到基板的第二表面; 设置在所述第一半导体芯片和所述基板之间的底部填充材料，封装所述焊料凸块; 第二半导体芯片，具有与第一表面相对的第一表面和第二表面，其中第二半导体芯片的第一表面安装到第一半导体芯片的第二表面; 以及从第二半导体芯片电耦合到衬底上的一组接合线柱的一组接合线。

公开(公告)号：US06365455B1

公开(公告)日：2002-04-02

申请号：US09092241

申请日：1998-06-05

Applicant: Wen-Doe Su ,  Thomas Chang ,  Kuo-Tung Sung ,  Mao Song Tseng ,  Shih-Chi Lai ,  Kun-Yu Sung ,  Liang-Chen Lin

Inventor： Wen-Doe Su ,  Thomas Chang ,  Kuo-Tung Sung ,  Mao Song Tseng ,  Shih-Chi Lai ,  Kun-Yu Sung ,  Liang-Chen Lin

IPC: H01L21336

CPC classification number: H01L27/11521 ,  H01L27/11524 ,  H01L29/66825

Abstract: An EPROM cell and a method that includes a gate structure having a sidewall spacer. The sidewall spacer is made by way of an amorphous or polycrystalline silicon layer, which is converted into an insulating layer such as silicon dioxide. Deposition of the amorphous or polycrystalline silicon layer is more accurate and produces a more uniform layer than conventional dielectric layer deposition.

Abstract translation: EPROM单元和包括具有侧壁间隔物的栅极结构的方法。 侧壁间隔物通过非晶或多晶硅层制成，其被转换成绝缘层，例如二氧化硅。 非晶或多晶硅层的沉积更精确，并且产生比常规介电层沉积更均匀的层。

公开(公告)号：US20100164091A1

公开(公告)日：2010-07-01

申请号：US12723433

申请日：2010-03-12

Applicant: Pei-Haw Tsao ,  Bill Kiang ,  Liang-Chen Lin ,  Pao-Kang Niu ,  I-Tai Liu

Inventor： Pei-Haw Tsao ,  Bill Kiang ,  Liang-Chen Lin ,  Pao-Kang Niu ,  I-Tai Liu

IPC: H01L25/065 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/3128 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/16225 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29298 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48475 ,  H01L2224/4848 ,  H01L2224/48499 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/85051 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/0401 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A system-in-package (SiP) package is provided. In one embodiment, the SiP package comprises a substrate having a first surface and a second surface opposite the first surface, the substrate having a set of bond wire studs on bond pads formed on the second surface thereof; a first semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the first semiconductor chip is mounted to the second surface of the substrate by means of solder bumps; an underfill material disposed between the first semiconductor chip and the substrate, encapsulating the solder bumps; a second semiconductor chip having a first surface and a second surface opposite the first surface, wherein the first surface of the second semiconductor chip is mounted to the second surface of the first semiconductor chip; and a set of bond wires electrically coupled from the second semiconductor chip to the set of bond wire studs on the substrate.

Abstract translation: 提供系统级封装（SiP）封装。 在一个实施例中，SiP封装包括具有第一表面和与第一表面相对的第二表面的衬底，衬底在其第二表面上形成的接合焊盘上具有一组接合线柱; 第一半导体芯片，具有与第一表面相对的第一表面和第二表面，其中第一半导体芯片的第一表面通过焊料凸块安装到基板的第二表面; 设置在所述第一半导体芯片和所述基板之间的底部填充材料，封装所述焊料凸块; 第二半导体芯片，具有与第一表面相对的第一表面和第二表面，其中第二半导体芯片的第一表面安装到第一半导体芯片的第二表面; 以及从第二半导体芯片电耦合到衬底上的一组接合线柱的一组接合线。

公开(公告)号：US07679180B2

公开(公告)日：2010-03-16

申请号：US11557372

申请日：2006-11-07

Applicant: Pei-Haw Tsao ,  Liang-Chen Lin ,  Pao-Kang Niu ,  I-Tai Liu ,  Bill Kiang

Inventor： Pei-Haw Tsao ,  Liang-Chen Lin ,  Pao-Kang Niu ,  I-Tai Liu ,  Bill Kiang

IPC: H01L23/12 ,  H05K7/00 ,  H01L21/44

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/056 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/14

Abstract: An improved via arrangement for a bonding pad structure is disclosed comprising an array of vias surrounded by a line via. The line via provides a barrier to cracks in the dielectric layer encompassing the via array. Although cracks are able to spread relatively unhindered between the vias of the via array, they are blocked by the line via and thus can not spread to neighboring regions of the chip or wafer. The line via can be provided in a variety of shapes and dimensions, to suit a desired application. Additionally, due to its substantially uninterrupted length, the line via provides added strength to the bond pad.

Abstract translation: 公开了一种用于焊盘结构的改进的通孔布置，其包括由线路通孔包围的通孔阵列。 线路通孔提供对包围通孔阵列的介电层中的裂纹的屏障。 虽然裂纹能够在通孔阵列的通孔之间相对不受阻碍地扩散，但是它们被线通孔阻挡，因此不能扩散到芯片或晶片的相邻区域。 线路通孔可以以各种形状和尺寸提供，以适应期望的应用。 另外，由于其基本上不间断的长度，线路通孔为接合焊盘提供附加的强度。

公开(公告)号：US07659632B2

公开(公告)日：2010-02-09

申请号：US11592220

申请日：2006-11-03

Applicant: Pei-Haw Tsao ,  Bill Kiang ,  Pao-Kang Niu ,  Liang-Chen Lin ,  I-Tai Liu

Inventor： Pei-Haw Tsao ,  Bill Kiang ,  Pao-Kang Niu ,  Liang-Chen Lin ,  I-Tai Liu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/10 ,  H01L23/3192 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Solder bump structures for semiconductor device packaging is provided. In one embodiment, a semiconductor device comprises a substrate having a bond pad and a first passivation layer formed thereabove, the first passivation layer having an opening therein exposing a portion of the bond pad. A metal pad layer is formed on a portion of the bond pad, wherein the metal pad layer contacts the bond pad. A second passivation layer is formed above the metal pad layer, the second passivation layer having an opening therein exposing a portion of the metal pad layer. A patterned and etched polyimide layer is formed on a portion of the metal pad layer and a portion of the second passivation layer. A conductive layer is formed above a portion of the etched polyimide layer and a portion of the metal pad layer, wherein the conductive layer contacts the metal pad layer. A conductive bump structure is connected to the conductive layer.

Abstract translation: 提供了用于半导体器件封装的焊接凸块结构。 在一个实施例中，半导体器件包括具有接合焊盘和在其上形成的第一钝化层的衬底，其中第一钝化层具有暴露焊接焊盘的一部分的开口。 在接合焊盘的一部分上形成金属焊盘层，其中金属焊盘层与接合焊盘接触。 第二钝化层形成在金属焊盘层的上方，第二钝化层在其中具有露出金属焊盘层的一部分的开口。 图案化和蚀刻的聚酰亚胺层形成在金属焊盘层的一部分和第二钝化层的一部分上。 在蚀刻的聚酰亚胺层的一部分和金属焊盘层的一部分上形成导电层，其中导电层与金属焊盘层接触。 导电凸块结构连接到导电层。

公开(公告)号：US20080274569A1

公开(公告)日：2008-11-06

申请号：US12217949

申请日：2008-07-10

Applicant: Pei-Haw Tsao ,  Pao-Kang Niu ,  Liang-Chen Lin ,  I. T. Liu

Inventor： Pei-Haw Tsao ,  Pao-Kang Niu ,  Liang-Chen Lin ,  I. T. Liu

IPC: H01L21/66

CPC classification number: H01L23/49816 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K3/3436 ,  H05K2201/094 ,  H05K2203/0465 ,  Y02P70/613

Abstract: A method for forming a semiconductor package provides a ball grid array, BGA, formed on a package substrate. The apices of the solder balls of the BGA are all at the same height, even if the package substrate is non-planar. Different solder ball pad sizes are used and tailored to compensate for non-planarity of the package substrate that may result from thermal warpage. Larger size solder ball pads are formed at relatively-high locations on the package substrate. An equal amount of solder is formed on each of the solder ball pads to produce solder balls having different heights and coplanar apices.

Abstract translation: 形成半导体封装的方法提供形成在封装衬底上的球栅阵列BGA。 即使封装衬底是非平面的，BGA的焊球的顶点都处于相同的高度。 不同的焊球尺寸被使用和定制以补偿可能由热翘曲引起的封装衬底的非平面性。 较大尺寸的焊球焊盘形成在封装衬底上相对较高的位置处。 在每个焊球垫上形成等量的焊料，以产生具有不同高度和共面顶点的焊球。