公开(公告)号：US07085180B2

公开(公告)日：2006-08-01

申请号：US10777596

申请日：2004-02-12

Applicant: Gregory J. Fredeman ,  Mark D. Jacunski ,  Toshiaki Kirihata ,  Matthew R. Wordeman

Inventor： Gregory J. Fredeman ,  Mark D. Jacunski ,  Toshiaki Kirihata ,  Matthew R. Wordeman

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11C29/4401 ,  G11C29/40 ,  G11C29/44 ,  G11C29/808 ,  G11C2029/0401 ,  G11C2029/2602

Abstract: A method for allocating redundancies during a multi-bank operation in a memory device which includes two or more redundancy domains is described. The method includes steps of enabling a pass/fail bit detection to activate a given bank. The pass/fail bit detection is prompted only for a selected domain and is disabled when it addresses other domains. By altering the domain selection, it is possible to enable a redundancy allocation for any domain regardless of the multi-bank operation. The method may preferably be realized by using a dynamic exclusive-OR logic with true and complement expected data pairs. When combined with simple pointer logic, the selection of domains may be generated internally, simplifying the built in self-test and other test control protocols, while at the same time tracking those that fail.

Abstract translation: 描述了在包括两个或更多个冗余域的存储器设备中在多存储体操作期间分配冗余的方法。 该方法包括启用通过/故障位检测来激活给定的存储体的步骤。 通过/失败位检测仅对选定的域提示，并且在寻址其他域时被禁用。 通过改变域选择，无论多行操作如何，都可以为任何域启用冗余分配。 该方法可以优选地通过使用具有真实和补充预期数据对的动态异或逻辑来实现。 当结合简单的指针逻辑时，可以内部生成域的选择，简化内置的自检和其他测试控制协议，同时跟踪失败的那些。

公开(公告)号：US06845059B1

公开(公告)日：2005-01-18

申请号：US10604109

申请日：2003-06-26

Applicant: Matthew R. Wordeman ,  John E. Barth ,  Toshiaki Kirihata

Inventor： Matthew R. Wordeman ,  John E. Barth ,  Toshiaki Kirihata

IPC: G11C7/10 ,  G11C8/16 ,  G11C11/406 ,  G11C11/4096 ,  G11C8/00

CPC classification number: G11C8/16 ,  G11C7/106 ,  G11C7/1087 ,  G11C11/40603 ,  G11C11/40615

Abstract: A memory architecture that utilizes single-ended dual-port destructive write memory cells and a local write-back buffer is described. Each cell has separate read and write ports that make it possible to read-out data from cells on one wordline in the array, and subsequently write-back to those cells while simultaneously reading-out the cell on another wordline in the array. By implementing an array of sense amplifiers such that one amplifier is coupled to each read bitline, and a latch receiving the result of the sensed data and delivering this data to the write data lines, it is possible to ‘pipeline’ the read-out and write-back phases of the read cycle. This allows for a write-back phase from one cycle to occur simultaneously with the read-out phase of another cycle. By extending the operation of the latch to accept data either from the sense amplifier, or from the memory data inputs, modified by the column address and masking bits, it is also possible to pipeline the read-out and the modify-write-back phases of a write cycle, allowing them to occur simultaneously. The architecture preferably employs a nondestructive read memory cell such as 2T or 3T gain cells, achieving an SRAM-like cycle and access times with a smaller and more SER immune memory cell.

Abstract translation: 描述了利用单端双端口破坏性写存储器单元和本地回写缓冲器的存储架构。 每个单元都具有单独的读取和写入端口，可以从阵列中的一个字线上的单元读出数据，随后将其写回到这些单元格，同时读出数组中另一个字线上的单元格。 通过实现读出放大器的阵列，使得一个放大器耦合到每个读取位线，以及一个接收感测数据的结果并将该数据传送到写入数据线的锁存器，可以“管理”读出和 读周期的回写阶段。 这允许来自一个周期的回写阶段与另一个周期的读出阶段同时发生。 通过扩展锁存器的操作以接受来自读出放大器或由存储器数据输入的数据，由列地址和掩码位修改，还可以管理读出和修改回写阶段 的写周期，允许它们同时发生。 该架构优选采用非破坏性读取存储器单元，例如2T或3T增益单元，通过较小和更多的SER免疫存储单元实现SRAM类周期和访问时间。

公开(公告)号：US06396324B1

公开(公告)日：2002-05-28

申请号：US09566311

申请日：2000-05-08

Applicant: Louis L. Hsu ,  Rajiv V. Joshi ,  Richard M. Parent ,  Matthew R. Wordeman

Inventor： Louis L. Hsu ,  Rajiv V. Joshi ,  Richard M. Parent ,  Matthew R. Wordeman

IPC: G06F104

CPC classification number: G11C7/225 ,  G06F1/04 ,  G11C7/22 ,  G11C7/222

Abstract: A clock system is provided capable of using an external system clock for driving at least one charge circuit of a semiconductor memory unit for restoring and refreshing a data array of the memory unit. The clock system, in one embodiment, includes a plurality of control circuits each having a clock select circuit which has as an input the external system clock, an internal clock generator circuit for generating an internal system clock, and a multiplexer. The multiplexer has as inputs an output of the clock select circuit, i.e., the external system clock, and an output of the internal clock generator circuit, i.e., the internal system clock. The multiplexer outputs either the external system clock or the internal system clock to the at least one charge circuit according to at least one control signal transmitted by a central processing unit to the clock select circuit.

Abstract translation: 提供一种时钟系统，其能够使用外部系统时钟来驱动用于恢复和刷新存储器单元的数据阵列的半导体存储器单元的至少一个充电电路。 在一个实施例中，时钟系统包括多个控制电路，每个控制电路具有时钟选择电路，该时钟选择电路具有作为输入的外部系统时钟，用于产生内部系统时钟的内部时钟发生器电路和多路复用器。 多路复用器具有时钟选择电路的输出，即外部系统时钟和内部时钟发生器电路的输出，即内部系统时钟的输入。 根据由中央处理单元发送到时钟选择电路的至少一个控制信号，多路复用器将外部系统时钟或内部系统时钟输出到至少一个充电电路。

公开(公告)号：US06255699B1

公开(公告)日：2001-07-03

申请号：US09561676

申请日：2000-05-01

Applicant: John A. Bracchitta ,  Jack A. Mandelman ,  Stephen A. Parke ,  Matthew R. Wordeman

Inventor： John A. Bracchitta ,  Jack A. Mandelman ,  Stephen A. Parke ,  Matthew R. Wordeman

IPC: H01L2976

CPC classification number: H01L21/823885 ,  H01L27/092

Abstract: A method of forming a pillar CMOS FET device, especially an inverter, and the device so formed is provided. The method includes forming abutting N wells and P wells in a silicon substrate and then forming N+ and P+ diffusions in the P and N wells respectively. A unitary pillar of the epitaxial silicon is grown on the substrate having a base at the substrate overlying both the N and P wells and preferably extending at least from said N+ diffusion to said P+ diffusion in said substrate. The pillar terminates at a distal end. An N well is formed on the side of the pillar overlying the N well in the substrate and a P well is formed on the side of the distal end of the pillar overlying the P well on the substrate and abuts the N well in the pillar. A P+ diffusion is formed in the N well in the pillar adjacent the distal end and a N+ diffusion is formed in the P well in the pillar adjacent the distal end. A gate insulator dioxide is formed over both sides of the pillar and gate electrodes are formed over the gate insulators.

Abstract translation: 提供了形成柱状CMOS FET器件，特别是逆变器的方法以及如此形成的器件。 该方法包括在硅衬底中形成邻接的N阱和P阱，然后分别在P阱和N阱中形成N +和P +扩散。 外延硅的单一支柱在衬底上生长，该基底在覆盖N和P阱的衬底上具有基底，并且优选地至少从所述N +扩散延伸到所述衬底中的所述P +扩散。 支柱在远端终止。 在衬底侧的N侧形成N阱，并且在衬底的远端侧的P侧上形成有P阱，该P阱覆盖在衬底上的P阱上，并且与衬垫中的N阱邻接。 在邻近远端的柱中的N阱中形成P +扩散，并且在靠近远端的柱中的P阱中形成N +扩散。 栅极绝缘体二氧化物形成在柱的两侧，栅电极形成在栅极绝缘体上。

公开(公告)号：US5894152A

公开(公告)日：1999-04-13

申请号：US878225

申请日：1997-06-18

Applicant: Mark A. Jaso ,  Jack A. Mandelman ,  William R. Tonti ,  Matthew R. Wordeman

Inventor： Mark A. Jaso ,  Jack A. Mandelman ,  William R. Tonti ,  Matthew R. Wordeman

IPC: H01L21/20 ,  H01L21/76 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC classification number: H01L21/84 ,  H01L21/7624 ,  H01L27/1203

Abstract: A semiconductor device having areas that are semiconductor on insulator ("SOI") and areas that are bulk, single crystalline semiconductive areas is provided in which conductive spacers may be formed to electrically connect the SOI areas to ground in order to overcome floating body effects that can occur with SOI. Additionally, insulative spacers may be formed on the surface of the conductive spacers to electrically isolate the SOI regions from the bulk regions. A novel method for making both of these products is provided in which the epitaxially grown, single crystalline bulk regions need not be selectively grown, because a sacrificial polishing layer is deposited, is also provided.

公开(公告)号：US5862058A

公开(公告)日：1999-01-19

申请号：US648745

申请日：1996-05-16

Applicant: Donald James Samuels ,  Matthew R. Wordeman

Inventor： Donald James Samuels ,  Matthew R. Wordeman

IPC: G03F1/36 ,  G03F7/20 ,  H01L21/027 ,  G06F17/50 ,  G06K9/03

CPC classification number: G03F7/70625 ,  G03F7/70441 ,  G03F1/36

Abstract: An optical proximity correction method and system are disclosed that allows for the correction of line width deviations caused by nonlinear lithography tools by calculating required chrome on glass line widths for a desired printed line. Line width correction is determined based only on the pitch of the line, defined as the width of the line and the distance to an adjacent line. Correction information is calculated from an aerial simulation and is then organized by pitch to provide a more efficient means of line correction.

Abstract translation: 公开了一种光学邻近校正方法和系统，其允许通过针对期望的印刷线计算玻璃线宽度上的所需铬，来校正由非线性光刻工具引起的线宽偏差。 线宽校正仅基于线的间距确定，定义为线的宽度和与相邻线的距离。 校正信息是从空中仿真计算出来的，然后通过俯仰来组织，以提供更有效的线路校正方法。

公开(公告)号：US5483179A

公开(公告)日：1996-01-09

申请号：US230265

申请日：1994-04-20

Applicant: Sang H. Dhong ,  Toshiaki Kirihata ,  Matthew R. Wordeman

Inventor： Sang H. Dhong ,  Toshiaki Kirihata ,  Matthew R. Wordeman

IPC: H03K17/687 ,  G05F3/24 ,  H03K19/0175 ,  H01L25/00

CPC classification number: G05F3/24

Abstract: A device for controlling the voltage across an NMOS pull-up transistor including a source node which may be exposed to a variable voltage. The device further includes a gate node which may be exposed to a variable voltage. A control portion regulates the voltage applied to the gate node, wherein a differential in voltage between the source node and the gate node is limited to a desired level.

Abstract translation: 用于控制跨越NMOS上拉晶体管的电压的装置，其包括可能暴露于可变电压的源节点。 该器件还包括可以暴露于可变电压的栅极节点。 控制部分调节施加到栅极节点的电压，其中源节点和栅极节点之间的电压差被限制到期望的电平。

公开(公告)号：US08476953B2

公开(公告)日：2013-07-02

申请号：US13217767

申请日：2011-08-25

Applicant: Joel A. Silberman ,  Matthew R. Wordeman

Inventor： Joel A. Silberman ,  Matthew R. Wordeman

IPC: G06F1/04 ,  H03K3/00

CPC classification number: H03L7/00 ,  G06F1/12 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

Abstract: There is provided a synchronization circuit for a 3D chip stack having multiple circuits and multiple strata interconnected using a first and a second stack-wide broadcast connection chain. The synchronization circuit includes the following, on each stratum. A synchronizer connected to the first connection chain receives an asynchronous signal therefrom and performs a synchronization to provide a synchronous signal. A driver is connected to the second chain for driving the synchronous signal. A latch connected to the second chain receives the synchronous signal driven by the driver on a same or different stratum within a next clock cycle from the synchronization to provide the stack-wide synchronous signal to a circuit on a same stratum. An output of a single driver on one stratum is selected at any given time for use by the latch on all strata.

公开(公告)号：US08476771B2

公开(公告)日：2013-07-02

申请号：US13217789

申请日：2011-08-25

Applicant: Michael R. Scheuermann ,  Joel A. Silberman ,  Matthew R. Wordeman

Inventor： Michael R. Scheuermann ,  Joel A. Silberman ,  Matthew R. Wordeman

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40 ,  H01L23/02 ,  H01L23/538

CPC classification number: H01L23/522 ,  H01L22/32 ,  H01L23/481 ,  H01L24/06 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06544

Abstract: There is provided a connection configuration for a multiple layer chip stack having two or more strata. Each of the two or more strata has multiple circuit components, a front-side and a back-side. The connection configuration includes a connection pair having as members a front-side connection and a backside connection unconnected to the front-side connection. The front-side connection and the backside connection are co-located with respect to each other on a given stratum from among the two or more strata, and are respectively connected to different ones of the multiple circuit components on the given stratum. At least one of the front-side connection and the backside connection is also connected to a particular one of the multiple circuit components on an adjacent stratum to the given stratum from among the two or more strata.

Abstract translation: 提供了具有两个或多个层的多层芯片堆叠的连接配置。 两个或更多个层中的每一个具有多个电路部件，即前侧和后侧。 连接配置包括具有作为前侧连接的构件和未连接到前侧连接的后侧连接的连接对。 前侧连接和后侧连接在两层或多层之间的给定层上彼此相对定位，并且分别连接到给定层上的多个电路组件中的不同电路组件。 前侧连接和背侧连接中的至少一个还连接到来自两个或更多个层中的给定层的相邻层上的多个电路部件中的特定一个。

公开(公告)号：US08466444B2

公开(公告)日：2013-06-18

申请号：US13406096

申请日：2012-02-27

Applicant: Lia Krusin-Elbaum ,  Dennis M. Newns ,  Matthew R. Wordeman

Inventor： Lia Krusin-Elbaum ,  Dennis M. Newns ,  Matthew R. Wordeman

IPC: H01L47/00

CPC classification number: H01L45/1226 ,  H01L27/24 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/148

Abstract: A switching circuit includes a plurality of three-terminal PCM switching devices connected between a voltage supply terminal and a sub-block of logic. Each of the switching devices includes a PCM disposed in contact between a first terminal and a second terminal, a heating device disposed in contact between the second terminal and a third terminal, the heating device positioned proximate the PCM, and configured to switch the conductivity of a transformable portion of the PCM between a lower resistance state and a higher resistance state; and an insulating layer configured to electrically isolate the heater from said PCM material, and the heater from the first terminal. The third terminal of a first of the PCM switching devices is coupled to a set/reset switch, and the third terminal of the remaining PCM switching devices is coupled to the second terminal of an adjacent PCM switching device in a cascade configuration.

Abstract translation: 开关电路包括连接在电压供给端子和逻辑子块之间的多个三端子PCM开关装置。 每个开关装置包括设置在第一端子和第二端子之间接触的PCM，加热装置，其设置成接触在第二端子和第三端子之间，加热装置位于PCM附近，并且被配置为切换 PCM的可变形部分在较低电阻状态和较高电阻状态之间; 以及绝缘层，其被配置为将加热器与所述PCM材料电隔离，并且所述加热器与所述第一端子电隔离。 第一个PCM开关器件的第三端子耦合到一个置位/复位开关，其余的PCM开关器件的第三个端子以级联配置耦合到一个相邻的PCM开关器件的第二个端子。