中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

29 records (took 0.019 seconds)

    Lateral diffusion field effect transistor with a trench field plate
    22.
    发明授权
    Lateral diffusion field effect transistor with a trench field plate 有权
    具有沟槽场板的横向扩散场效应晶体管

    公开(公告)号：US07956412B2

    公开(公告)日：2011-06-07

    申请号：US11950001

    申请日：2007-12-04

    Applicant: Natalie B. Feilchenfeld ,  Jeffrey P. Gambino ,  Louis D. Lanzerotti ,  Benjamin T. Voegeli ,  Steven H. Voldman ,  Michael J. Zierak

    Inventor： Natalie B. Feilchenfeld ,  Jeffrey P. Gambino ,  Louis D. Lanzerotti ,  Benjamin T. Voegeli ,  Steven H. Voldman ,  Michael J. Zierak

    IPC: H01L29/417

    CPC classification number: H01L29/7825 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/66704 ,  H01L29/7816

    Abstract: A dielectric material layer is formed on a bottom surface and sidewalls of a trench in a semiconductor substrate. The silicon oxide layer forms a drift region dielectric on which a field plate is formed. Shallow trench isolation may be formed prior to formation of the drift region dielectric, or may be formed utilizing the same processing steps as the formation of the drift region dielectric. A gate dielectric layer is formed on exposed semiconductor surfaces and a gate conductor layer is formed on the gate dielectric layer and the drift region dielectric. The field plate may be electrically tied to the gate electrode, may be an independent electrode having an external bias, or may be a floating electrode. The field plate biases the drift region to enhance performance and extend allowable operating voltage of a lateral diffusion field effect transistor during operation.

    Abstract translation: 介电材料层形成在半导体衬底的沟槽的底表面和侧壁上。 氧化硅层形成漂移区电介质，在其上形成场板。 可以在形成漂移区电介质之前形成浅沟槽隔离，或者可以利用与形成漂移区电介质相同的处理步骤来形成。 在暴露的半导体表面上形成栅极电介质层，并且在栅极介电层和漂移区电介质上形成栅极导体层。 场板可以电连接到栅电极，可以是具有外部偏置的独立电极，或者可以是浮置电极。 场板偏置漂移区域以增强性能并且在操作期间延长横向扩散场效应晶体管的允许工作电压。

    BIPOLAR TRANSISTOR WITH RAISED EXTRINSIC SELF-ALIGNED BASE USING SELECTIVE EPITAXIAL GROWTH FOR BICMOS INTEGRATION
    23.
    发明申请
    BIPOLAR TRANSISTOR WITH RAISED EXTRINSIC SELF-ALIGNED BASE USING SELECTIVE EPITAXIAL GROWTH FOR BICMOS INTEGRATION 有权
    使用选择性外延生长用于BICMOS整合的具有增强的自对准基底的双极晶体管

    公开(公告)号：US20110062548A1

    公开(公告)日：2011-03-17

    申请号：US12949108

    申请日：2010-11-18

    Applicant: Natalie B. Feilchenfeld ,  Bradley A. Orner ,  Benjamin T. Voegeli

    Inventor： Natalie B. Feilchenfeld ,  Bradley A. Orner ,  Benjamin T. Voegeli

    IPC: H01L27/06 ,  H01L21/8249

    CPC classification number: H01L29/7302 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/66287

    Abstract: High performance bipolar transistors with raised extrinsic self-aligned base are integrated into a BiCMOS structure containing CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS devices and by forming an extrinsic base through selective epitaxy, the effect of topographical variations is minimized during a lithographic patterning of the extrinsic base. Also, by not employing any chemical mechanical planarization process during the fabrication of the bipolar structures, complexity of process integration is reduced. Internal spacers or external spacers may be formed to isolate the base from the emitter. The pad layers, the intrinsic base layer, and the extrinsic base layer form a mesa structure with coincident outer sidewall surfaces.

    Abstract translation: 具有凸起的外部自对准基极的高性能双极晶体管集成到包含CMOS器件的BiCMOS结构中。 通过形成焊盘层并相对于先前存在的CMOS器件的源极和漏极提高本征基极层的高度，并且通过选择性外延形成外部基极，在外部基极的光刻图案化期间，拓扑变化的影响被最小化。 而且，通过在双极结构的制造期间不采用任何化学机械平面化工艺，工艺集成的复杂性降低。 可以形成内部间隔物或外部隔离物以将基底与发射器隔离。 垫层，本征基层和非本征基层形成具有重合的外侧壁表面的台面结构。

    Optimized Device Isolation
    26.
    发明申请
    Optimized Device Isolation 有权
    优化设备隔离

    公开(公告)号：US20100117122A1

    公开(公告)日：2010-05-13

    申请号：US12269073

    申请日：2008-11-12

    Applicant: John J. Benoit ,  David S. Collins ,  Natalie B. Feilchenfeld ,  Michael L. Gautsch ,  Xuefeng Liu ,  Robert M. Rassel ,  Stephen A. St Onge ,  James A. Slinkman

    Inventor： John J. Benoit ,  David S. Collins ,  Natalie B. Feilchenfeld ,  Michael L. Gautsch ,  Xuefeng Liu ,  Robert M. Rassel ,  Stephen A. St Onge ,  James A. Slinkman

    IPC: H01L27/092 ,  H01L27/085

    CPC classification number: H01L21/761 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0921 ,  H01L27/0928

    Abstract: A structure for a semiconductor device includes an isolated MOSFET (e.g., NFET) having triple-well technology adjacent to an isolated PFET which itself is adjacent to an isolated NFET. The structure includes a substrate in which is formed a deep n-band region underneath any n-wells, p-wells and p-band regions within the substrate. One p-band region is formed above the deep n-band region and underneath the isolated p-well for the isolated MOSFET, while another p-band region is formed above the deep n-band region and underneath all of the p-wells and n-wells, including those that are part of the isolated PFET and NFET devices within the substrate. The n-wells for the isolated MOSFET are connected to the deep n-band region. The resulting structure provides for improved device isolation and reduction of noise propagating from the substrate to the FETs while maintaining the standard CMOS spacing layout spacing rules and electrical biasing characteristics both external and internal to the triple-well isolation regions.

    Abstract translation: 用于半导体器件的结构包括具有三阱技术的隔离MOSFET（例如，NFET），其邻近隔离PFET，其本身与隔离的NFET相邻。 该结构包括其中在衬底内的任何n阱，p阱和p带区之下形成深n波段区的衬底。 一个p带区域形成在深n波段区域之上，隔离的MOSFET的隔离p阱下面，而另一个p波段区域形成在深n波段区域上方，并在所有p阱区域下方， n阱，包括作为衬底内的隔离PFET和NFET器件的一部分的n阱。 隔离MOSFET的n阱连接到深n波段区域。 所得到的结构提供改进的器件隔离和降低从衬底传播到FET的噪声，同时保持三阱隔离区域的外部和内部的标准CMOS间隔布局间隔规则和电偏置特性。

    LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH A TRENCH FIELD PLATE
    28.
    发明申请
    LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH A TRENCH FIELD PLATE 有权
    横向扩展场效应晶体管与TRENCH现场板

    公开(公告)号：US20090140343A1

    公开(公告)日：2009-06-04

    申请号：US11950001

    申请日：2007-12-04

    Applicant: Natalie B. Feilchenfeld ,  Jeffrey P. Gambino ,  Louis D. Lanzerotti ,  Benjamin T. Voegeli ,  Steven H. Voldman ,  Michael J. Zierak

    Inventor： Natalie B. Feilchenfeld ,  Jeffrey P. Gambino ,  Louis D. Lanzerotti ,  Benjamin T. Voegeli ,  Steven H. Voldman ,  Michael J. Zierak

    IPC: H01L29/78 ,  H01L21/02

    CPC classification number: H01L29/7825 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/66704 ,  H01L29/7816

    Abstract: A dielectric material layer is formed on a bottom surface and sidewalls of a trench in a semiconductor substrate. The silicon oxide layer forms a drift region dielectric on which a field plate is formed. Shallow trench isolation may be formed prior to formation of the drift region dielectric, or may be formed utilizing the same processing steps as the formation of the drift region dielectric. A gate dielectric layer is formed on exposed semiconductor surfaces and a gate conductor layer is formed on the gate dielectric layer and the drift region dielectric. The field plate may be electrically tied to the gate electrode, may be an independent electrode having an external bias, or may be a floating electrode. The field plate biases the drift region to enhance performance and extend allowable operating voltage of a lateral diffusion field effect transistor during operation.

    Abstract translation: 介电材料层形成在半导体衬底的沟槽的底表面和侧壁上。 氧化硅层形成漂移区电介质，在其上形成场板。 可以在形成漂移区电介质之前形成浅沟槽隔离，或者可以利用与形成漂移区电介质相同的处理步骤来形成。 在暴露的半导体表面上形成栅极电介质层，并且在栅极介电层和漂移区电介质上形成栅极导体层。 场板可以电连接到栅电极，可以是具有外部偏置的独立电极，或者可以是浮置电极。 场板偏置漂移区域以增强性能并且在操作期间延长横向扩散场效应晶体管的允许工作电压。

    LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH ASYMMETRIC GATE DIELECTRIC PROFILE
    29.
    发明申请
    LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH ASYMMETRIC GATE DIELECTRIC PROFILE 有权
    具有不对称栅介质剖面的横向扩散场效应晶体管

    公开(公告)号：US20090108347A1

    公开(公告)日：2009-04-30

    申请号：US11924650

    申请日：2007-10-26

    Applicant: James W. Adkisson ,  Natalie B. Feilchenfeld ,  Jeffrey P. Gambino ,  Benjamin T. Voegeli ,  Michael J. Zierak

    Inventor： James W. Adkisson ,  Natalie B. Feilchenfeld ,  Jeffrey P. Gambino ,  Benjamin T. Voegeli ,  Michael J. Zierak

    IPC: H01L29/78

    CPC classification number: H01L29/7835 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/512 ,  H01L29/66659

    Abstract: A gate stack comprising a uniform thickness gate dielectric, a gate electrode, and an oxygen-diffusion-resistant gate cap is formed on a semiconductor substrate. Thermal oxidation is performed only on the drain side of the gate electrode, while the source side is protected from thermal oxidation. A thermal oxide on the drain side sidewall of the gate electrode is integrally formed with a graded thickness silicon oxide containing gate dielectric, of which the thickness monotonically increases from the source side to the drain side. The thickness profile may be self-aligned to the drain side edge of the gate electrode, or may have a portion with a self-limiting thickness. The graded thickness profile may be advantageously used to form a lateral diffusion metal oxide semiconductor field effect transistor providing an enhanced performance.

    Abstract translation: 在半导体基板上形成包括均匀厚度的栅极电介质，栅电极和耐氧扩散栅极盖的栅极堆叠。 仅在栅电极的漏极侧进行热氧化，同时防止源极侧受热氧化。 栅电极的漏极侧壁上的热氧化物与层状厚度的含氧化硅的栅极电介质整体形成，其厚度从源极侧向漏极侧单调增加。 厚度分布可以与栅电极的漏极侧边缘自对准，或者可以具有自限制厚度的部分。 梯度厚度分布可以有利地用于形成提供增强性能的横向扩散金属氧化物半导体场效应晶体管。

Patent Agency Ranking