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公开(公告)号：US08125834B2
公开(公告)日：2012-02-28
申请号：US12619581
申请日：2009-11-16
CPC分类号： G11C5/04 , G06F3/0613 , G06F3/0659 , G06F3/0679 , G06F12/0676 , G06F13/1668 , G06F13/4243 , G11C5/00 , G11C5/066 , G11C8/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A memory system includes an array of solid state memory devices which are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are is accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is mounted on a multi-bit mount and assigned an array address by it an array mount. An A memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array particular mount multi-bit configuration is used to unconditionally select the device mounted thereon. A reserved predefined address broadcast over the device bus deselects all previously selected memory devices. Read performance is enhanced by a read streaming technique in which while a current chunk of data is being serialized and shifted out of the memory subsystem devices to the controller module, the controller module is also setting up the address for the next chunk of data to begin to address the memory system.
摘要翻译： 存储器系统包括固态存储器件的阵列，其经由具有极少线的器件总线与控制器模块通信并处于控制器模块的控制之下。 这形成了集成电路大容量存储系统，其被设想来替代大容量存储系统，例如计算机系统中的磁盘驱动器存储器。 命令，地址和数据信息被串行化为组件字符串，并在控制器模块和存储器件阵列之间传输之前被多路复用。 串行化信息伴随着一个控制信号，以帮助整理复用的组件。 阵列中的每个存储器件都安装在多位安装上，并通过阵列安装分配阵列地址。 通过在设备总线上广播的适当地址来选择存储器件，而不需要通常的专用选择信号。 使用保留阵列特定安装多位配置来无条件地选择安装在其上的装置。 通过设备总线广播的保留的预定义地址取消选择所有先前选择的存储设备。 读取性能通过读取流技术得到增强，其中当当前块的数据被序列化并从存储器子系统设备移出到控制器模块时，控制器模块还设置下一个数据块开始的地址 寻址内存系统。
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公开(公告)号：US20100064098A1
公开(公告)日：2010-03-11
申请号：US12619581
申请日：2009-11-16
CPC分类号： G11C5/04 , G06F3/0613 , G06F3/0659 , G06F3/0679 , G06F12/0676 , G06F13/1668 , G06F13/4243 , G11C5/00 , G11C5/066 , G11C8/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A memory system includes an array of solid state memory devices which are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are is accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is mounted on a multi-bit mount and assigned an array address by it an array mount. An A memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array particular mount multi-bit configuration is used to unconditionally select the device mounted thereon. A reserved predefined address broadcast over the device bus deselects all previously selected memory devices. Read performance is enhanced by a read streaming technique in which while a current chunk of data is being serialized and shifted out of the memory subsystem devices to the controller module, the controller module is also setting up the address for the next chunk of data to begin to address the memory system.
摘要翻译： 存储器系统包括固态存储器件的阵列，其经由具有极少线的器件总线与控制器模块通信并处于控制器模块的控制之下。 这形成了集成电路大容量存储系统，其被设想来替代大容量存储系统，例如计算机系统中的磁盘驱动器存储器。 命令，地址和数据信息被串行化为组件字符串，并在控制器模块和存储器件阵列之间传输之前被多路复用。 串行化信息伴随着一个控制信号，以帮助整理复用的组件。 阵列中的每个存储器件都安装在多位安装上，并通过阵列安装分配阵列地址。 通过在设备总线上广播的适当地址来选择存储器件，而不需要通常的专用选择信号。 使用保留阵列特定安装多位配置来无条件地选择安装在其上的装置。 通过设备总线广播的保留的预定义地址取消选择所有先前选择的存储设备。 读取性能通过读取流技术得到增强，其中当当前块的数据被序列化并从存储器子系统设备移出到控制器模块时，控制器模块还设置下一个数据块开始的地址 寻址内存系统。
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公开(公告)号：US07444458B2
公开(公告)日：2008-10-28
申请号：US11079407
申请日：2005-03-14
申请人： Robert D. Norman , Vinod C. Lakhani
发明人： Robert D. Norman , Vinod C. Lakhani
IPC分类号： G06F12/06
CPC分类号： G06F13/1694 , G06F12/0661
摘要： A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an array of memory cells, addressing circuitry used to address the cells and an address storage circuit which stores a local address unique to each of the memory devices. The local addresses are sequentially assigned to the memory devices by selecting a first one of the devices and forwarding an address assign command to the selected device. A command decoder, having detected the address assign command, will permit a local address placed on the bus by the controller to be loaded into the selected memory device. This sequence will continue until all of the memory devices have been assigned local addresses at which time the memory devices can be accessed to perform memory read, program, erase and other operations.
摘要翻译： 一种存储器系统，具有存储器控制器和通过系统总线连接到控制器的几个单独的存储器件。 存储器件各自包括存储器单元阵列，用于寻址单元的寻址电路和存储每个存储器件唯一的本地地址的地址存储电路。 通过选择设备中的第一个并将地址分配命令转发到所选择的设备，将本地地址依次分配给存储器设备。 已经检测到地址分配命令的命令解码器将允许由控制器放置在总线上的本地地址被加载到所选择的存储器件中。 该序列将继续，直到所有存储器件都被分配了本地地址，此时可以访问存储器件以执行存储器读取，编程，擦除和其他操作。
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公开(公告)号：US07437631B2
公开(公告)日：2008-10-14
申请号：US10917870
申请日：2004-08-13
申请人： Daniel L. Auclair , Jeffrey Craig , John S. Mangan , Robert D. Norman , Daniel C. Guterman , Sanjay Mehrotra
发明人： Daniel L. Auclair , Jeffrey Craig , John S. Mangan , Robert D. Norman , Daniel C. Guterman , Sanjay Mehrotra
IPC分类号： G11C29/00
CPC分类号： G11C29/028 , G06F11/1068 , G06F11/1072 , G06F2201/81 , G11C16/04 , G11C16/10 , G11C16/3431 , G11C29/50 , G11C29/50004 , G11C29/52 , G11C2029/5004 , G11C2029/5006
摘要： Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.
摘要翻译： 正常使用固态存储器（如EEPROM或闪存EEPROM）时会发生软错误。 存储器单元的编程阈值电压从原来的预期电平漂移导致软错误。 在正常读取期间，最初不容易检测到该误差，直到累积漂移变得如此严重以致其发展为硬错误。 数据可能会丢失，如果这些硬错误足够的可以在存储器中发出可用的纠错码。 一种存储器件及其技术能够在整个使用存储器件的过程中检测这些漂移并且将每个存储器单元的阈值电压基本上保持在其预期的水平，从而抵抗将软错误发展成硬错误。
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公开(公告)号：US07397713B2
公开(公告)日：2008-07-08
申请号：US10348739
申请日：2003-01-21
IPC分类号： G11C7/00
CPC分类号： G11C29/26 , G06F3/0601 , G06F3/0616 , G06F3/064 , G06F3/0652 , G06F3/0679 , G06F3/068 , G06F3/0688 , G06F11/1068 , G06F12/0246 , G06F12/0802 , G06F12/0804 , G06F12/0866 , G06F12/0875 , G06F12/123 , G06F2003/0694 , G06F2212/2022 , G06F2212/312 , G06F2212/7201 , G06F2212/7203 , G06F2212/7205 , G06F2212/7207 , G06F2212/7208 , G11C7/1039 , G11C8/12 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/10 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C29/00 , G11C29/34 , G11C29/52 , G11C29/765 , G11C29/82 , G11C2211/5621 , G11C2211/5634 , G11C2211/5643 , G11C2216/18
摘要： A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.
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公开(公告)号：US07209401B2
公开(公告)日：2007-04-24
申请号：US11415771
申请日：2006-05-02
CPC分类号： H03L1/00 , H03K3/011 , H03K3/0315
摘要： An apparatus compensates for voltage and temperature variations on an integrated circuit with: a voltage sensor having a digital voltage output; a temperature sensor having a digital temperature output; a register coupled to the voltage sensor and the temperature sensor, the register adapted to concatenate the digital voltage output and the temperature output into an address output; and a memory device having an address input coupled to the address output of the register, the memory device being adapted to store one or more corrective vectors.
摘要翻译： 一种装置利用具有数字电压输出的电压传感器补偿集成电路上的电压和温度变化; 具有数字温度输出的温度传感器; 寄存器，耦合到电压传感器和温度传感器，寄存器适于将数字电压输出和温度输出连接成地址输出; 以及具有耦合到寄存器的地址输出的地址输入的存储器件，所述存储器件适于存储一个或多个校正矢量。
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公开(公告)号：US07209013B2
公开(公告)日：2007-04-24
申请号：US11359187
申请日：2006-02-22
CPC分类号： H04Q9/00 , G01K15/00 , G05D23/1917 , G05D23/24 , H03L1/00
摘要： A self-calibrating integrated circuit includes a processor having at least one analog function used with the processor; one or more sensors adapted to sense one or more environmental parameters of the at least one analog function; and a solid state memory being configured to store the one or more environmental parameters of the at least one analog function.
摘要翻译： 自校准集成电路包括具有与处理器一起使用的至少一个模拟功能的处理器; 适于感测所述至少一个模拟功能的一个或多个环境参数的一个或多个传感器; 以及固态存储器，其被配置为存储所述至少一个模拟功能的所述一个或多个环境参数。
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公开(公告)号：US07190617B1
公开(公告)日：2007-03-13
申请号：US09103056
申请日：1998-06-23
IPC分类号： G11C11/34
CPC分类号： G11C29/26 , G06F3/0614 , G06F3/0616 , G06F3/064 , G06F3/0652 , G06F3/0679 , G06F11/1068 , G06F12/0246 , G06F12/0804 , G06F12/123 , G06F2212/1036 , G06F2212/312 , G06F2212/7201 , G06F2212/7203 , G06F2212/7205 , G11C7/1039 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/16 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C29/00 , G11C29/34 , G11C29/52 , G11C29/765 , G11C29/82 , G11C2211/5621 , G11C2211/5634 , G11C2211/5643
摘要： A system of Flash EEprom chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.
摘要翻译： 具有控制电路的Flash EEprom芯片的系统用作诸如由磁盘驱动器提供的非易失性存储器。 改进包括选择性多扇区擦除，其中Flash扇区的任何组合可以一起被擦除。 所选组合中的选择扇区也可以在擦除操作期间被取消选择。 另一个改进是使用替代细胞重新映射和替换有缺陷的细胞的能力。 一旦检测到有缺陷的单元，就会自动执行重新映射。 当Flash扇区的缺陷数量变大时，整个扇区被重新映射。 另一个改进是使用写高速缓存来减少写入闪存EEPROM存储器的数量，从而最小化对器件进行过多写/擦循环的应力。
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公开(公告)号：US06853259B2
公开(公告)日：2005-02-08
申请号：US09930822
申请日：2001-08-15
CPC分类号： H03L1/00 , H03K3/011 , H03K3/0315
摘要： An apparatus compensates for voltage and temperature variations on an integrated circuit with: a voltage sensor having a digital voltage output; a temperature sensor having a digital temperature output; a register coupled to the voltage sensor and the temperature sensor, the register adapted to concatenate the digital voltage output and the temperature output into an address output; and a memory device having an address input coupled to the address output of the register, the memory device being adapted to store one or more corrective vectors.
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30.发明授权公开(公告)号：US06628537B1
公开(公告)日：2003-09-30
申请号：US10197027
申请日：2002-07-16
IPC分类号： G11C502
CPC分类号： G06F3/0601 , G06F13/385 , G06F2003/0694 , G06K7/0047 , G06K19/07732 , G06K19/07741 , G06K19/07743 , G11C5/04 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83385 , H05K1/141 , H05K3/3421 , H05K7/1431 , H05K2201/10159 , H05K2201/10462 , H05K2201/10484 , H05K2203/1572 , H01L2924/00014 , H01L2924/00
摘要： A very small computer memory card is densely packed with a large number of flash EEPROM integrated circuit chips. A computer memory system provides for the ability to removably connect one or more of such cards with a common controller circuit that interfaces between the memory cards and a standard computer system bus. Alternately, each card can be provided with the necessary controller circuitry and thus is connectable directly to the computer system bus. An electronic system is described for a memory system and its controller within a single memory card. In a preferred physical arrangement, the cards utilize a main circuit board with a plurality of sub-boards attached thereto on both sides, each sub-board carrying several integrated circuit chips.
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