公开(公告)号：US20240095502A1

公开(公告)日：2024-03-21

申请号：US18470281

申请日：2023-09-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pierre Demaj ,  Laurent Folliot

IPC: G06N3/0464

CPC classification number: G06N3/0464

Abstract: An artificial neural network includes a unit cell. The unit cell includes a first binary two-dimensional convolution layer configured to receive an input tensor and to generate a first tensor. A first batch normalization layer is configured to receive the first tensor and to generate a second tensor. A concatenation layer is configured to generate a third tensor by concatenating the input tensor and the second tensor. A second binary two-dimensional convolution layer is configured to receive the third tensor and to generate a fourth tensor. A second batch normalization layer is configured to generate an output tensor based on the fourth tensor.

公开(公告)号：US20240081160A1

公开(公告)日：2024-03-07

申请号：US18506383

申请日：2023-11-10

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe BOIVIN ,  Simon JEANNOT

IPC: H10N70/20 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/231 ,  H10B63/30 ,  H10B63/80 ,  H10N70/011 ,  H10N70/061 ,  H10N70/253 ,  H10N70/823 ,  H10N70/826 ,  H10N70/8265 ,  H10N70/8413 ,  H10N70/8828 ,  G11C13/0004

Abstract: A memory cell includes a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element. The memory cell is formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor. The gate is formed on the active layer and has a lateral flank covered with a second insulating layer. The variable-resistance element includes a first layer covering a lateral flank of the active layer in a trench formed through the active layer along the lateral flank of the gate and reaching the first insulating layer, and a second layer made of a variable-resistance material.

公开(公告)号：US11921834B2

公开(公告)日：2024-03-05

申请号：US16249804

申请日：2019-01-16

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Fabrice Marinet

IPC: G06F21/00 ,  B41J2/175 ,  G06F21/44 ,  G06K15/02 ,  G06F21/73

CPC classification number: G06F21/44 ,  B41J2/17546 ,  B41J2/17566 ,  G06K15/1822 ,  G06F21/73 ,  G06F2221/2129

Abstract: A method of authenticating a first electronic circuit includes generating a first signature using the first electronic circuit, the generating of the first signature being based on states of a plurality of electric nodes distributed within the first electronic circuit. A second signature is generated using a second electronic circuit, the generating of the second signature being based on states of a plurality of electric nodes distributed within the second electronic circuit. The first signature is compared to the second signature. The first electronic circuit is authenticated based on the comparison of the first signature to the second signature.

公开(公告)号：US11894657B2

公开(公告)日：2024-02-06

申请号：US17360381

申请日：2021-06-28

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics S.r.l.

Inventor： Romeo Letor ,  Vanni Poletto ,  Antoine Pavlin ,  Nadia Lecci ,  Alfio Russo

IPC: H01S5/062 ,  H03K5/07 ,  H01S5/026

CPC classification number: H01S5/06216 ,  H01S5/0261 ,  H03K5/07

Abstract: An embodiment pulse generator circuit comprises a first electronic switch coupled between first and second nodes, and a second electronic switch coupled between the second node and a reference node. An LC resonant circuit comprising an inductance and a capacitance is coupled between the first and reference nodes along with charge circuitry comprises a further inductance in a current flow line between a supply node and an intermediate node in the LC resonant circuit. Drive circuitry of the electronic switches repeats, during a sequence of switching cycles, charge time intervals, wherein the capacitance in the LC resonant circuit is charged via the charge circuit, and pulse generation time intervals, wherein a pulsed current is provided to the load via the first and second nodes. The charge and pulse generation time intervals are interleaved with oscillation time intervals where the LC resonant circuit oscillates at a resonance frequency.

公开(公告)号：US11889397B2

公开(公告)日：2024-01-30

申请号：US17649146

申请日：2022-01-27

Applicant: STMicroelectronics (Rousset) SAS ,  STMICROELECTRONICS GMBH

Inventor： Thierry Meziache ,  Pierre Rizzo ,  Alexandre Charles ,  Juergen Boehler

IPC: H04W4/80 ,  G06K7/00 ,  G06K7/10 ,  H04B5/00

CPC classification number: H04W4/80 ,  G06K7/0008 ,  G06K7/10237 ,  G06K7/10247 ,  H04B5/0031

Abstract: A device, including a main element and a set of at least two auxiliary elements, said main element including a master SWP interface, each auxiliary element including a slave SWP interface connected to said master SWP interface of said NFC element through a controllably switchable SWP link and management means configured to control said SWP link switching for selectively activating at once only one slave SWP interface on said SWP link.

公开(公告)号：US11855633B2

公开(公告)日：2023-12-26

申请号：US17827515

申请日：2022-05-27

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Jean-Francois Link ,  Mark Wallis ,  Joran Pantel

IPC: H03K19/17724 ,  H03K19/173 ,  H03K19/17704 ,  H03K3/0233 ,  H03K19/096

CPC classification number: H03K19/17724 ,  H03K3/0233 ,  H03K19/096 ,  H03K19/1737 ,  H03K19/17708

Abstract: An integrated circuit includes a programmable logic array. The programmable logic array incudes a plurality of logic elements arranged in rows and columns. Each logic element includes a direct output and a synchronized output. The direct output of each logic element is coupled to all other logic elements of higher rank, but is not coupled to logic elements of lower rank.

公开(公告)号：US20230401306A1

公开(公告)日：2023-12-14

申请号：US18207292

申请日：2023-06-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Laurent TABARIES

IPC: G06F21/44 ,  G06F21/78

CPC classification number: G06F21/44 ,  G06F21/78

Abstract: The electronic control unit includes a communication circuit adapted to receive intelligent transport system messages, an authentication circuit designed to authenticate the received messages, a non-volatile memory configured to record the authenticated received messages, and a secure element. The secure element includes a blacklist of automatically excluded senders and is configured to directly reject a received message from a sender on the blacklist without authentication using the authentication circuit. Alternatively, the secure element includes a whitelist of automatically allowed senders and is configured to directly record a received message from a sender on the whitelist in the non-volatile memory without authentication using the authentication circuit.

公开(公告)号：US11838024B2

公开(公告)日：2023-12-05

申请号：US17119865

申请日：2020-12-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Tramoni ,  Jimmy Fort

IPC: H03K3/0233 ,  G06F1/3287 ,  H03K17/687

CPC classification number: H03K3/02337 ,  G06F1/3287 ,  H03K17/687

Abstract: An embodiment provides a circuit of cyclic activation of an electronic function including a hysteresis comparator controlling the charge of a capacitive element powering the function.

公开(公告)号：US11818883B2

公开(公告)日：2023-11-14

申请号：US17540029

申请日：2021-12-01

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki ,  Mathieu Lisart ,  Benoit Froment

IPC: H10B20/00 ,  H01L23/00 ,  G11C16/04

CPC classification number: H10B20/367 ,  G11C16/0466 ,  H01L23/57

Abstract: The present description concerns a ROM including at least one first rewritable memory cell.

公开(公告)号：US20230359368A1

公开(公告)日：2023-11-09

申请号：US18192237

申请日：2023-03-29

Applicant: STMicroelectronics(Rousset) SAS

Inventor： Mark Wallis ,  Laurent Lestringand

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/0637 ,  G06F3/0673

Abstract: In accordance with an embodiment, a system-on-chip includes: a memory circuit comprising a first memory region accessible with a first access right level and a second memory region accessible with the first access right level or a second access right level, at least one first peripheral having the first access right level, at least one second peripheral having the second access right level; and a direct memory access circuit configured to generate direct memory accesses, wherein the direct memory access circuit includes at least one first direct memory access controller having the first access right level and at least one second direct memory access controller having the second access right level.