公开(公告)号：US20060220709A1

公开(公告)日：2006-10-05

申请号：US11320846

申请日：2005-12-30

Applicant: Sang-Jin Byeon ,  Kee-Teok Park

Inventor： Sang-Jin Byeon ,  Kee-Teok Park

IPC: H03L7/00

CPC classification number: H03K17/223 ,  G11C5/143

Abstract: There is provided a circuit and a method for generating a power up signal. The circuit for generating a power up signal, includes an external power voltage divider for dividing a magnitude of an external power voltage so as to output the divided voltage, an external power voltage detector for activating a detection signal when the output voltage of the external power voltage divider reaches a preset level, and a power up signal generator for outputting a power up signal according to the detection signal and a first internal power voltage. Herein, the power up signal is generated when the internal power voltage as well as the external power voltage reaches a sufficient level so that a power up signal skew may be reduced to stabilize its operation and enhance reliability of a device.

Abstract translation: 提供了一种用于产生上电信号的电路和方法。 用于产生上电信号的电路包括：外部电源分压器，用于分压外部电源电压的大小以输出分压;外部电源电压检测器，用于在外部电源的输出电压时激活检测信号 分压器达到预设电平;以及上电信号发生器，用于根据检测信号和第一内部电源电压输出上电信号。 这里，当内部电源电压和外部电源电压达到足够的电平时，产生上电信号，从而可以减少上电信号偏移以稳定其操作并提高装置的可靠性。

公开(公告)号：US20130241314A1

公开(公告)日：2013-09-19

申请号：US13602257

申请日：2012-09-03

Applicant: Tae Sik YUN ,  Sang Jin BYEON

Inventor： Tae Sik YUN ,  Sang Jin BYEON

IPC: H03K17/00

CPC classification number: H01L25/0657 ,  G01R31/2882 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H03K17/14 ,  H03K19/00369 ,  Y10T307/826

Abstract: A semiconductor apparatus includes: a slave chip including a signal transfer unit configured to determine whether or not to transfer an input signal in response to a chip select signal; a master chip including a replica circuit unit having the same configuration as the signal transfer unit and a signal output unit configured to receive an output signal of the signal transfer unit and an output signal of the replica circuit unit and generate an output signal in response to the control signal; a first through-chip via vertically formed through the slave chip, and having one end connected to the master chip to receive the input signal and the other end connected to the signal transfer unit; and a second through-chip via vertically formed through the slave chip, and having one end connected to the signal transfer unit and the other end connected to the signal output unit.

Abstract translation: 半导体装置包括：从芯片，包括信号传送单元，配置为响应于芯片选择信号确定是否传送输入信号; 包括具有与信号传送单元相同配置的复制电路单元的主芯片和被配置为接收信号传送单元的输出信号和复制电路单元的输出信号的信号输出单元，并响应于 控制信号; 通过垂直形成的从芯片的第一通芯片，并且一端连接到主芯片以接收输入信号，另一端连接到信号传送单元; 以及通过垂直形成的从芯片的第二通芯片，并且其一端连接到信号传送单元，另一端连接到信号输出单元。

公开(公告)号：US20130043933A1

公开(公告)日：2013-02-21

申请号：US13592902

申请日：2012-08-23

Applicant: Sang-Jin BYEON

Inventor： Sang-Jin BYEON

IPC: G05F1/10

CPC classification number: G11C5/147

Abstract: A semiconductor device including an internal voltage generator circuit that provides an internal voltage having a different level depending on the operation speed is provided. The semiconductor device includes an internal voltage generator circuit configured to receive operation speed information to generate an internal voltage having a different level depending on the operation speed; and an internal circuit operated using the internal voltage.

公开(公告)号：US08369122B2

公开(公告)日：2013-02-05

申请号：US12838332

申请日：2010-07-16

Applicant: Sang Jin Byeon ,  Jae Jin Lee

Inventor： Sang Jin Byeon ,  Jae Jin Lee

IPC: G11C5/00 ,  G11C5/02 ,  G11C5/06 ,  G11C7/00 ,  G11C8/00

CPC classification number: H03L7/00

Abstract: A semiconductor apparatus has a plurality of chips stacked therein. Read control signals for controlling read operations of the plurality of chips are synchronized with a reference clock such that the time taken from the application of a read command to the output of data for each of the plurality of chips is maintained substantially the same.

Abstract translation: 半导体装置具有堆叠在其中的多个芯片。 用于控制多个芯片的读取操作的读取控制信号与参考时钟同步，使得从应用读取命令到多个芯片中的每一个的数据输出所花费的时间保持基本相同。

公开(公告)号：US20120249229A1

公开(公告)日：2012-10-04

申请号：US13236970

申请日：2011-09-20

Applicant: Jae-Bum KO ,  Jong-Chern Lee ,  Sang-Jin Byeon

Inventor： Jae-Bum KO ,  Jong-Chern Lee ,  Sang-Jin Byeon

IPC: H01L25/00

CPC classification number: G11C8/12

Abstract: A semiconductor integrated circuit includes a plurality of semiconductor chips respectively selected in response to a plurality of chip selection signals, and a chip selection signal generator configured to generate the chip selection signals in response to one first control signal for deciding whether to drive the semiconductor chips and at least one second control signal for selecting at least one semiconductor chip from among the semiconductor chips.

Abstract translation: 半导体集成电路包括分别响应于多个芯片选择信号选择的多个半导体芯片，以及芯片选择信号发生器，被配置为响应于用于决定是否驱动半导体芯片的一个第一控制信号产生芯片选择信号 以及用于从半导体芯片中选择至少一个半导体芯片的至少一个第二控制信号。

公开(公告)号：US08279702B2

公开(公告)日：2012-10-02

申请号：US12840966

申请日：2010-07-21

Applicant: Jae Bum Ko ,  Sang Jin Byeon

Inventor： Jae Bum Ko ,  Sang Jin Byeon

IPC: G11C8/00

CPC classification number: H01L25/0657 ,  G11C8/12 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor apparatus includes an individual-chip-designating-code setting block configured to generate a plurality of sets of individual-chip-designating-codes which have different code values or in which at least two sets of individual-chip-designating-codes have the same code value, in response to a plurality of chip fuse signals; a control block configured to generate a plurality of enable control signals in response to the plurality of chip fuse signals and most significant bits of the plurality of sets of individual-chip-designating-codes; and an individual chip activation block configured to compare individual-chip-designating-codes of the plurality of sets of individual-chip-designating-codes excluding the most significant bits, with chip selection addresses in response to the plurality of enable control signals, and enable one of a plurality of individual-chip-activation-signals depending upon a comparison result.

Abstract translation: 一种半导体装置，包括单芯片指定码设置块，被配置为生成具有不同码值的多组独立芯片指定码，或者至少两组独立芯片指定码具有 相应的代码值，响应于多个芯片熔丝信号; 控制块，被配置为响应于所述多个芯片熔丝信号和所述多组独立芯片指定代码中的最高有效位而产生多个使能控制信号; 以及单独的芯片激活块，其被配置为响应于所述多个使能控制信号，将所述多个独立芯片指定码组中排除最高有效位的各个芯片指定码与芯片选择地址进行比较，以及 根据比较结果使能多个个别芯片激活信号中的一个。

公开(公告)号：US20120124408A1

公开(公告)日：2012-05-17

申请号：US13166094

申请日：2011-06-22

Applicant: Sang Jin BYEON ,  Jae Bum Ko

Inventor： Sang Jin BYEON ,  Jae Bum Ko

IPC: G06F1/06 ,  H01L23/498

CPC classification number: G11C5/04 ,  G11C16/20 ,  G11C2029/4402 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2924/00014

Abstract: A semiconductor apparatus may comprise: a first chip ID generation unit configured to receive an enable signal through a first through-silicon via and a clock signal through a second through-silicon via and generate a first chip ID signal and a delayed enable signal; a second chip ID generation unit configured to receive the delayed enable signal through a third through-silicon via from the first chip ID generation unit and the clock signal and generate a second chip ID signal; a first chip selection signal generation unit configured to receive the first chip ID signal and a main ID signal and generate a first chip selection signal; and a second chip selection signal generation unit configured to receive the second chip ID signal and the main ID signal and generate a second chip selection signal.

Abstract translation: 半导体装置可以包括：第一芯片ID生成单元，被配置为通过第一穿通硅通孔接收使能信号和通过第二通过硅通孔的时钟信号，并生成第一芯片ID信号和延迟使能信号; 第二芯片ID生成单元，被配置为通过来自第一芯片ID生成单元的第三通过硅通孔和时钟信号接收延迟使能信号，并生成第二芯片ID信号; 第一芯片选择信号生成单元，被配置为接收第一芯片ID信号和主ID信号，并生成第一芯片选择信号; 以及第二芯片选择信号生成单元，被配置为接收第二芯片ID信号和主ID信号，并生成第二芯片选择信号。

公开(公告)号：US20120057413A1

公开(公告)日：2012-03-08

申请号：US12948874

申请日：2010-11-18

Applicant: Tae Sik YUN ,  Hyung Dong Lee ,  Jun Gi Choi ,  Sang Jin Byeon ,  Sang Hoon Shin

Inventor： Tae Sik YUN ,  Hyung Dong Lee ,  Jun Gi Choi ,  Sang Jin Byeon ,  Sang Hoon Shin

IPC: G11C8/18 ,  G11C29/00 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C7/22 ,  G11C7/222 ,  G11C29/006 ,  G11C29/023

Abstract: A semiconductor memory apparatus includes a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer in length to a target clock cycle than the first clock; a DLL input clock generation unit configured to output one of the first clock and the second clock as a DLL input clock according to a DLL select signal; and an address/command input clock generation unit configured to output one of the first clock and the second clock as an AC input clock according to the enable signal.

Abstract translation: 一种半导体存储装置，包括：时钟控制单元，被配置为当使能信号被激活时接收第一时钟，并产生具有与第一时钟相对于目标时钟周期更长的周期的第二时钟; DLL输入时钟生成单元，被配置为根据DLL选择信号将第一时钟和第二时钟中的一个作为DLL输入时钟输出; 以及地址/命令输入时钟生成单元，被配置为根据使能信号将第一时钟和第二时钟中的一个作为AC输入时钟输出。

公开(公告)号：US20120007624A1

公开(公告)日：2012-01-12

申请号：US12914424

申请日：2010-10-28

Applicant: Sang-Jin Byeon ,  Jong-Chern Lee

Inventor： Sang-Jin Byeon ,  Jong-Chern Lee

IPC: G01R31/26

CPC classification number: G11C11/4072 ,  G06F2213/0038 ,  G11C7/10 ,  G11C8/12 ,  G11C11/4076 ,  G11C16/20

Abstract: A semiconductor system for identifying stacked chips includes a first semiconductor chip and a plurality of second semiconductor chips. The first semiconductor chip generates a plurality of counter codes by using an internal clock or an external input clock and transmits slave address signals and the counter codes through a through-chip via. The second semiconductor chips are given corresponding identifications (IDs) by latching the counter codes for a predetermined delay time, compare the latched counter codes with the slave address signals, and communicate data with the first semiconductor chip through the through-chip via according to the comparison result.

Abstract translation: 用于识别堆叠芯片的半导体系统包括第一半导体芯片和多个第二半导体芯片。 第一半导体芯片通过使用内部时钟或外部输入时钟产生多个计数器代码，并且通过片上通孔发送从地址信号和计数器代码。 通过在预定的延迟时间内锁存计数器代码来对第二半导体芯片进行相应的标识（ID），将锁存的计数器代码与从地址信号进行比较，并根据通过芯片通过与第一半导体芯片通信数据 比较结果。

公开(公告)号：US20110267137A1

公开(公告)日：2011-11-03

申请号：US12840966

申请日：2010-07-21

Applicant: Jae Bum KO ,  Sang Jin BYEON

Inventor： Jae Bum KO ,  Sang Jin BYEON

IPC: H03K19/003

CPC classification number: H01L25/0657 ,  G11C8/12 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor apparatus includes an individual-chip-designating-code setting block configured to generate a plurality of sets of individual-chip-designating-codes which have different code values or in which at least two sets of individual-chip-designating-codes have the same code value, in response to a plurality of chip fuse signals; a control block configured to generate a plurality of enable control signals in response to the plurality of chip fuse signals and most significant bits of the plurality of sets of individual-chip-designating-codes; and an individual chip activation block configured to compare individual-chip-designating-codes of the plurality of sets of individual-chip-designating-codes excluding the most significant bits, with chip selection addresses in response to the plurality of enable control signals, and enable one of a plurality of individual-chip-activation-signals depending upon a comparison result.

Abstract translation: 一种半导体装置，包括单芯片指定码设置块，被配置为生成具有不同码值的多组独立芯片指定码，或者至少两组独立芯片指定码具有 相应的代码值，响应于多个芯片熔丝信号; 控制块，被配置为响应于所述多个芯片熔丝信号和所述多组独立芯片指定代码中的最高有效位而产生多个使能控制信号; 以及单独的芯片激活块，其被配置为响应于所述多个使能控制信号，将所述多个独立芯片指定码组中排除最高有效位的各个芯片指定码与芯片选择地址进行比较，以及 根据比较结果使能多个个别芯片激活信号中的一个。