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    MOSFET formed on a strained silicon layer
    21.
    发明授权
    MOSFET formed on a strained silicon layer 有权
    形成在应变硅层上的MOSFET

    公开(公告)号：US07557388B2

    公开(公告)日：2009-07-07

    申请号：US11398118

    申请日：2006-04-05

    Applicant: Sun-Ghil Lee ,  Young-Pil Kim ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Young-Eun Lee

    Inventor： Sun-Ghil Lee ,  Young-Pil Kim ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Young-Eun Lee

    IPC: H01L31/00 ,  H01L35/26 ,  H01L31/117

    CPC classification number: C30B29/06 ,  C30B15/00

    Abstract: A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.

    Abstract translation: 公开了一种形成在应变硅层上的半导体器件及其制造方法。 根据本发明，在单晶硅衬底上形成第一硅锗层; 第二硅锗层形成在第一硅锗层上，第二硅锗层的锗浓度在约1重量％至约15重量％的范围内，基于第二硅锗层的总重量 ; 在第二硅锗层上形成应变硅层; 在应变硅层的第一部分处形成隔离层; 在应变硅层上形成栅极结构; 并且源极/漏极区域形成在与栅极结构相邻的应变硅层的第二部分处以形成晶体管。

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING STRESS MEMORIZATION TECHNIQUE
    23.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING STRESS MEMORIZATION TECHNIQUE 有权
    使用应力记忆技术制造半导体器件的方法

    公开(公告)号：US20130115742A1

    公开(公告)日：2013-05-09

    申请号：US13495062

    申请日：2012-06-13

    Applicant: Seok-Hoon KIM ,  Sang-Su KIM ,  Chung-Geun KOH ,  Sun-Ghil LEE ,  Jin-Yeong JOE

    Inventor： Seok-Hoon KIM ,  Sang-Su KIM ,  Chung-Geun KOH ,  Sun-Ghil LEE ,  Jin-Yeong JOE

    IPC: H01L21/336

    CPC classification number: H01L29/7847 ,  H01L21/26506 ,  H01L21/26593 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7843

    Abstract: The manufacturing a semiconductor device includes providing a substrate supporting a gate electrode, amorphizing and doping the source/drain regions located on both sides of the gate electrode by performing a pre-amorphization implant (PAI) process and implanting C or N into the source/drain regions in or separately from the PAI process, forming a stress inducing layer on the substrate to cover the amorphized source/drain regions, and subsequently recrystallizing the source/drain regions by annealing the substrate. The stress inducing layer may then be removed. Also, the C or N may be implanted into the entirety of the source/drain regions after the regions have been amorphized, or only into upper portions of the amorphized source/drain regions.

    Abstract translation: 制造半导体器件包括提供支撑栅电极的衬底，通过执行预非晶化注入（PAI）工艺并且将C或N注入到源/漏区中来对位于栅电极的两侧的源/漏区进行非晶化和掺杂， 漏极区域或与PAI工艺分离，在衬底上形成应力诱导层以覆盖非晶化源极/漏极区域，并且随后通过对衬底退火来使源极/漏极区域再结晶。 然后可以去除应力诱导层。 此外，在区域已经非晶化之后，或仅仅在非晶化源极/漏极区域的上部，C或N可以被注入到整个源极/漏极区域中。

    Semiconductor memory devices having vertical channel transistors and related methods
    25.
    发明授权
    Semiconductor memory devices having vertical channel transistors and related methods 有权
    具有垂直沟道晶体管的半导体存储器件及相关方法

    公开(公告)号：US08008698B2

    公开(公告)日：2011-08-30

    申请号：US12198266

    申请日：2008-08-26

    Applicant: Deok-hyung Lee ,  Sun-ghil Lee ,  Si-young Choi ,  Byeong-chan Lee ,  Seung-hun Lee

    Inventor： Deok-hyung Lee ,  Sun-ghil Lee ,  Si-young Choi ,  Byeong-chan Lee ,  Seung-hun Lee

    IPC: H01L27/108

    CPC classification number: H01L27/10894 ,  H01L27/0207 ,  H01L27/10876 ,  H01L27/10882 ,  H01L27/10885

    Abstract: A semiconductor memory device may include a semiconductor substrate with an active region extending in a first direction parallel with respect to a surface of the semiconductor substrate. A pillar may extend from the active region in a direction perpendicular with respect to the surface of the semiconductor substrate with the pillar including a channel region on a sidewall thereof. A gate insulating layer may surround a sidewall of the pillar, and a word line may extend in a second direction parallel with respect to the surface of the semiconductor substrate. Moreover, the first and second directions may be different, and the word line may surround the sidewall of the pillar so that the gate insulating layer is between the word line and the pillar. A contact plug may be electrically connected to the active region and spaced apart from the word line, and a bit line may be electrically connected to the active region through the contact plug with the plurality of bit lines extending in the first direction. Related methods are also discussed.

    Abstract translation: 半导体存储器件可以包括具有在相对于半导体衬底的表面平行的第一方向上延伸的有源区的半导体衬底。 柱可以在与半导体衬底的表面垂直的方向上从有源区延伸，其中柱在其侧壁上包括沟道区。 栅极绝缘层可以围绕柱的侧壁，并且字线可以在相对于半导体衬底的表面平行的第二方向上延伸。 此外，第一和第二方向可以不同，并且字线可以围绕柱的侧壁，使得栅极绝缘层在字线和柱之间。 接触插塞可以电连接到有源区并与字线间隔开，并且位线可以通过接触插塞电连接到有源区，多个位线沿第一方向延伸。 还讨论了相关方法。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    26.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20090239348A1

    公开(公告)日：2009-09-24

    申请号：US12478345

    申请日：2009-06-04

    Applicant: Sun-Ghil Lee ,  Young-Pil Kim ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Young-Eun Lee

    Inventor： Sun-Ghil Lee ,  Young-Pil Kim ,  Yu-Gyun Shin ,  Jong-Wook Lee ,  Young-Eun Lee

    IPC: H01L21/336

    CPC classification number: C30B29/06 ,  C30B15/00

    Abstract: A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.

    Abstract translation: 公开了一种形成在应变硅层上的半导体器件及其制造方法。 根据本发明，在单晶硅衬底上形成第一硅锗层; 第二硅锗层形成在第一硅锗层上，第二硅锗层的锗浓度在约1重量％至约15重量％的范围内，基于第二硅锗层的总重量 ; 在第二硅锗层上形成应变硅层; 在应变硅层的第一部分处形成隔离层; 在应变硅层上形成栅极结构; 并且源极/漏极区域形成在与栅极结构相邻的应变硅层的第二部分处以形成晶体管。

    Semiconductor Memory Devices Having Vertical Channel Transistors and Related Methods
    27.
    发明申请
    Semiconductor Memory Devices Having Vertical Channel Transistors and Related Methods 有权
    具有垂直沟道晶体管的半导体存储器件及相关方法

    公开(公告)号：US20090121268A1

    公开(公告)日：2009-05-14

    申请号：US12198266

    申请日：2008-08-26

    Applicant: Deok-hyung Lee ,  Sun-ghil Lee ,  Si-young Choi ,  Byeong-chan Lee ,  Seung-hun Lee

    Inventor： Deok-hyung Lee ,  Sun-ghil Lee ,  Si-young Choi ,  Byeong-chan Lee ,  Seung-hun Lee

    IPC: H01L27/108 ,  H01L21/8242

    CPC classification number: H01L27/10894 ,  H01L27/0207 ,  H01L27/10876 ,  H01L27/10882 ,  H01L27/10885

    Abstract: A semiconductor memory device may include a semiconductor substrate with an active region extending in a first direction parallel with respect to a surface of the semiconductor substrate. A pillar may extend from the active region in a direction perpendicular with respect to the surface of the semiconductor substrate with the pillar including a channel region on a sidewall thereof. A gate insulating layer may surround a sidewall of the pillar, and a word line may extend in a second direction parallel with respect to the surface of the semiconductor substrate. Moreover, the first and second directions may be different, and the word line may surround the sidewall of the pillar so that the gate insulating layer is between the word line and the pillar. A contact plug may be electrically connected to the active region and spaced apart from the word line, and a bit line may be electrically connected to the active region through the contact plug with the plurality of bit lines extending in the first direction. Related methods are also discussed.

    Abstract translation: 半导体存储器件可以包括具有在相对于半导体衬底的表面平行的第一方向上延伸的有源区的半导体衬底。 柱可以在与半导体衬底的表面垂直的方向上从有源区延伸，其中柱在其侧壁上包括沟道区。 栅极绝缘层可以围绕柱的侧壁，并且字线可以在相对于半导体衬底的表面平行的第二方向上延伸。 此外，第一和第二方向可以不同，并且字线可以围绕柱的侧壁，使得栅极绝缘层在字线和柱之间。 接触插塞可以电连接到有源区并与字线间隔开，并且位线可以通过接触插塞电连接到有源区，多个位线沿第一方向延伸。 还讨论了相关方法。

    Fin field effect transistors having multi-layer fin patterns
    28.
    发明授权
    Fin field effect transistors having multi-layer fin patterns 失效
    鳍场效应晶体管具有多层翅片图案

    公开(公告)号：US07323710B2

    公开(公告)日：2008-01-29

    申请号：US10870743

    申请日：2004-06-17

    Applicant: Young-Pil Kim ,  Sun-Ghil Lee ,  Si-Young Choi

    Inventor： Young-Pil Kim ,  Sun-Ghil Lee ,  Si-Young Choi

    IPC: H01L29/06 ,  H01L31/00

    CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/78687

    Abstract: A fin field effect transistor has a fin pattern protruding from a semiconductor substrate. The fin pattern includes first semiconductor patterns and second semiconductor patterns which are stacked. The first and second semiconductor patterns have lattice widths that are greater than a lattice width of the substrate in at least one direction. In addition, the first and second semiconductor patterns may be alternately stacked to increase the height of the fin pattern, such that one of the first and second patterns can reduce stress from the other of the first and second patterns. The first and second semiconductor patterns may be formed of strained silicon and silicon-germanium, where the silicon-germanium patterns can reduce stress from the strained silicon patterns. Therefore, both the number of carriers and the mobility of carriers in the transistor channel may be increased, improving performance of the fin field effect transistor. Related methods are also discussed.

    Abstract translation: 鳍状场效应晶体管具有从半导体衬底突出的鳍状图案。 鳍状图案包括堆叠的第一半导体图案和第二半导体图案。 第一和第二半导体图案具有在至少一个方向上大于衬底的晶格宽度的晶格宽度。 此外，第一和第二半导体图案可以交替堆叠以增加鳍片图案的高度，使得第一和第二图案中的一个可以减小来自第一和第二图案中的另一个的应力。 第一和第二半导体图案可以由应变硅和硅 - 锗形成，其中硅 - 锗图案可以减小应变硅图案的应力。 因此，可以增加晶体管沟道中的载流子数和载流子的迁移率，从而提高鳍式场效应晶体管的性能。 还讨论了相关方法。

    Magnetic random access memory using bipolar junction transistor, and method for fabricating the same
    29.
    发明授权
    Magnetic random access memory using bipolar junction transistor, and method for fabricating the same 有权
    使用双极晶体管的磁性随机存取存储器

    公开(公告)号：US06657270B2

    公开(公告)日：2003-12-02

    申请号：US10127364

    申请日：2002-04-22

    Applicant: Chang Shuk Kim ,  Hee Bok Kang ,  Sun Ghil Lee

    Inventor： Chang Shuk Kim ,  Hee Bok Kang ,  Sun Ghil Lee

    IPC: H01L2982

    CPC classification number: H01L27/226 ,  B82Y10/00 ,  G11C11/16 ,  G11C11/5607

    Abstract: A magnetic random access memory (MRAM) is disclosed. The MRAM may include a semiconductor substrate serving as a base of a bipolar junction transistor; an emitter and a collector of the bipolar junction transistor provided at an active region of the semiconductor substrate; an MTJ cell positioned at the active region between the emitter and the collector, separately from the emitter and the collector by a predetermined distance; and a word line provided on the MTJ cell. The MRAM may also include a bit line contacting the collector; and a reference voltage line contacting the emitter. As a result, the constitution and fabrication process of the MRAM are simplified to improve productivity and properties of the device.

    Abstract translation: 公开了一种磁性随机存取存储器（MRAM）。 MRAM可以包括用作双极结晶体管的基极的半导体衬底; 设置在半导体衬底的有源区的双极结型晶体管的发射极和集电极; 位于发射极和集电极之间的有源区域的MTJ单元与发射极和集电极分开预定距离; 和在MTJ单元上提供的字线。 MRAM还可以包括接收收集器的位线; 以及与发射极接触的参考电压线。 结果，简化了MRAM的结构和制造过程，以提高设备的生产率和性能。

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