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    Repeater of global input/output line
    21.
    发明授权
    Repeater of global input/output line 有权
    全球输入/输出线路中继器

    公开(公告)号：US07924634B2

    公开(公告)日：2011-04-12

    申请号：US12217203

    申请日：2008-07-01

    Applicant: Tae Jin Kang ,  Seung Hyun Ryu

    Inventor： Tae Jin Kang ,  Seung Hyun Ryu

    IPC: G11C7/10

    CPC classification number: H04B1/48

    Abstract: A repeater of a global input/output line includes a data transmitter including first and second drivers for outputting data signals of the global input/output line through different transmission routes in response to a transmission direction control signal, and a third driver for driving the global input/output line in response to an output signal of the data transmitter.

    Abstract translation: 全局输入/输出线的中继器包括数据发射器，其包括用于响应于传输方向控制信号通过不同传输路由输出全局输入/输出线的数据信号的第一和第二驱动器，以及用于驱动全局 响应于数据发射器的输出信号的输入/输出线。

    ELECTRICALLY CONDUCTIVE METAL COMPOSITE EMBROIDERY YARN AND EMBROIDERED CIRCUIT USING THEREOF
    23.
    发明申请
    ELECTRICALLY CONDUCTIVE METAL COMPOSITE EMBROIDERY YARN AND EMBROIDERED CIRCUIT USING THEREOF 有权
    电导电金属复合绣花线及其使用的绣花线

    公开(公告)号：US20100199901A1

    公开(公告)日：2010-08-12

    申请号：US12668930

    申请日：2008-07-30

    Applicant: Tae-Jin Kang ,  Byung Duck Kim ,  Young Seung Chi ,  Jung Sim Roh

    Inventor： Tae-Jin Kang ,  Byung Duck Kim ,  Young Seung Chi ,  Jung Sim Roh

    IPC: D05C17/00 ,  D07B1/06 ,  D02G3/02

    CPC classification number: D02G3/12 ,  A41D27/00 ,  D02G3/28 ,  D02G3/441 ,  D05C7/06 ,  D10B2331/04 ,  H05K1/038 ,  H05K2201/0281 ,  H05K2201/029

    Abstract: The present invention relates to an electrically conductive metal composite embroidery yarn and embroidered circuit using thereof which may be applicable to smart textiles. More particularly, this invention relates to an electrically conductive metal composite embroidery yarn and embroidered circuit for smart textiles which can be used as power supply and signal transmission lines. The present invention provides an embroidered circuit which consists of a metal composite embroidery yarn and a dielectric fabric substrate, wherein the electrically conductive metal composite embroidery yarn is embroidered on the dielectric fabric substrate to form a circuit.

    Abstract translation: 本发明涉及可应用于智能纺织品的导电金属复合刺绣线及其使用的绣花电路。 更具体地，本发明涉及可用作电源和信号传输线的智能纺织品的导电金属复合刺绣线和绣花电路。 本发明提供了一种由金属复合刺绣纱线和电介质织物基材组成的绣花线路，其中将导电金属复合刺绣纱线绣在电介质织物基底上以形成电路。

    Shift circuit capable of reducing current consumption by controlling latch operation
    24.
    发明申请
    Shift circuit capable of reducing current consumption by controlling latch operation 审中-公开
    移位电路能够通过控制闩锁操作来减少电流消耗

    公开(公告)号：US20090185654A1

    公开(公告)日：2009-07-23

    申请号：US12317217

    申请日：2008-12-18

    Applicant: Tae Jin Kang

    Inventor： Tae Jin Kang

    IPC: G11C19/00

    CPC classification number: G11C19/00 ,  G11C19/28

    Abstract: Disclosed is a shift circuit capable of reducing current consumption and circuit area and increasing the operation speed. The shift circuit includes a transfer unit for transferring input data to a first node in response to a clock signal, and a latch unit for latching the data on the first node in response to a clock signal.

    Abstract translation: 公开了一种能够减少电流消耗和电路面积并提高操作速度的移位电路。 移位电路包括用于响应于时钟信号将输入数据传送到第一节点的传送单元和用于响应于时钟信号将数据锁存在第一节点上的锁存单元。

    OBJECTIVE EVALUATION OF FABRIC PILLING USING STEREOVISION AND MEASURING APPARATUS
    25.
    发明申请
    OBJECTIVE EVALUATION OF FABRIC PILLING USING STEREOVISION AND MEASURING APPARATUS 审中-公开
    使用立体测量和测量装置进行织物打孔的目标评估

    公开(公告)号：US20080063261A1

    公开(公告)日：2008-03-13

    申请号：US11939822

    申请日：2007-11-14

    Applicant: Tae-Jin KANG

    Inventor： Tae-Jin KANG

    IPC: G06K9/00

    CPC classification number: G06T7/0004 ,  G01N21/8851 ,  G01N21/8901 ,  G01N21/8983 ,  G01N2021/1772 ,  G01N2021/1785 ,  G01N2021/8861 ,  G01N2021/8896 ,  G01N2021/8908 ,  G06T2207/30124

    Abstract: The present invention relates to a objective measurement of fabric pillings, to a measurement apparatus which includes stereovision technique using CCD cameras, captures the 3-dimensional contours of fabric pilling and defines the degree of pilling occurrences. This invention is composed of; a step to scan the surface of a pilling-containing fabric specimen which is laid on the table and translated in the right angle of the projector laser beam; a step to reconstruct the scanned fabric surface data in to a 3D image; a step to convert the 3D image into a binary image using height-threshold method and number, area, density of pillings acquired from standard pictures; a step to calculate the x, y coordinates and height values of each and every area of the specimen; a step to regress the relationship between the height values of the pilling fabric specimen and the actual height values. Thus the measurement of fabric surface pillings using stereovision method which is composed of slit beam laser projector and a couple of CCD cameras can be a fast and accurate evaluation method regardless of the fabric's color and pattern shape.

    Abstract translation: 本发明涉及一种对织物支柱的客观测量，包括使用CCD照相机的立体视觉技术的测量装置，捕捉织物起球的三维轮廓并定义起球发生的程度。 本发明由 扫描放置在桌子上并且以投影仪激光束的直角平移的起球含织物样品的表面的步骤; 将扫描的织物表面数据重建成3D图像的步骤; 使用高度阈值法和从标准图像获取的数量，面积，密度的密度将3D图像转换为二进制图像的步骤; 计算样本每个区域的x，y坐标和高度值的步骤; 退化起毛织物样品的高度值与实际高度值之间的关系的步骤。 因此，无论织物的颜色和图案形状如何，使用由狭缝光束激光投影仪和两个CCD照相机组成的使用立体视觉方法的织物表面丸的测量可以是快速和准确的评估方法。

    Bank selectable parallel test circuit and parallel test method thereof
    26.
    发明授权
    Bank selectable parallel test circuit and parallel test method thereof 有权
    银行可选并行测试电路及其并行测试方法

    公开(公告)号：US07136315B2

    公开(公告)日：2006-11-14

    申请号：US11085173

    申请日：2005-03-22

    Applicant: Tae Jin Kang

    Inventor： Tae Jin Kang

    IPC: G11C29/00

    CPC classification number: G11C8/12 ,  G11C29/26 ,  G11C2029/2602

    Abstract: A parallel test circuit performs a selective test on a specific bank. The bank selectable parallel test circuit comprises a bank selecting control unit and a plurality of bank selecting units. The bank selecting control unit outputs a test mode control signal for selecting a test mode in response to a parallel test signal for controlling a parallel test and a compression test signal for controlling bank selection in the parallel test. Each of the plurality of bank selecting units, which correspond one by one to banks, selectively activates the corresponding banks in response to the test mode control signal and a bank selecting control signal.

    Abstract translation: 并行测试电路对特定的银行进行选择性测试。 存储体可选并行测试电路包括存储体选择控制单元和多个存储体选择单元。 存储体选择控制单元响应用于并行测试的并行测试信号和用于在并行测试中控制存储体选择的压缩测试信号，输出用于选择测试模式的测试模式控制信号。 响应于测试模式控制信号和存储体选择控制信号，对应于一个一个存储体的多个存储体选择单元中的每一个选择性地激活相应的存储体。

    Semiconductor device for reducing the number of probing pad used during wafer test and method for testing the same
    27.
    发明授权
    Semiconductor device for reducing the number of probing pad used during wafer test and method for testing the same 有权
    用于减少在晶片测试期间使用的探测器的数量的半导体器件及其测试方法

    公开(公告)号：US07002364B2

    公开(公告)日：2006-02-21

    申请号：US10738691

    申请日：2003-12-17

    Applicant: Tae Jin Kang ,  Woon Bok Lee

    Inventor： Tae Jin Kang ,  Woon Bok Lee

    IPC: G01R31/28

    CPC classification number: G01R31/3172 ,  G01R31/31715 ,  G01R31/318505 ,  G01R31/318511

    Abstract: The present invention relates to a semiconductor device and a method for testing the same capable of reducing the number of probing pads used during wafer test. The semiconductor device includes a select circuit connected between a plurality of internal circuits to be tested and a single probing pad, for transmitting test signals inputted from the probing pads to any one of the plurality of the internal circuits according to a test mode signal generated in a wafer test mode. It is possible to reduce the number of the probing pads in the integrated circuit used for connection to a probe for contact of a probe card during wafer test. It is therefore possible to reduce test time.

    Abstract translation: 半导体器件及其测试方法技术领域本发明涉及能够减少在晶片测试期间使用的探针焊盘数量的半导体器件及其测试方法。 半导体器件包括连接在待测试的多个内部电路和单个探测焊盘之间的选择电路，用于根据在多个内部电路中产生的测试模式信号将从探测焊盘输入的测试信号发送到多个内部电路中的任何一个 晶圆测试模式。 在晶片测试期间，可以减少用于与用于探针卡接触的探针连接的集成电路中的探测器的数量。 因此可以减少测试时间。

    Apparatus and method for data outputting
    28.
    发明申请
    Apparatus and method for data outputting 有权
    用于数据输出的装置和方法

    公开(公告)号：US20050243614A1

    公开(公告)日：2005-11-03

    申请号：US11178561

    申请日：2005-07-12

    Applicant: Tae-Jin Kang ,  Bong-Hwa Jeong

    Inventor： Tae-Jin Kang ,  Bong-Hwa Jeong

    IPC: G11C5/00 ,  G11C7/10 ,  G11C7/22

    CPC classification number: G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222

    Abstract: An data output circuit for outputting a data stored in a core of a semiconductor memory device includes a clock generator for generating a rising clock and a falling clock by using an external clock, a clock repeater for outputting the rising clock and the falling clock as one of a high voltage clock and a low voltage clock in response to an external voltage level check signal, a level shifter for outputting a high voltage data generated by shifting the data synchronized with the high voltage clock, a data carrier for outputting a low voltage data synchronized with the low voltage clock, and a data repeater for outputting one of the high voltage data and the low voltage data in response to the external voltage level check signal.

    Abstract translation: 用于输出存储在半导体存储器件的核心中的数据的数据输出电路包括用于通过使用外部时钟产生上升时钟和下降时钟的时钟发生器，用于输出上升时钟和下降时钟的时钟转发器 响应于外部电压电平检查信号的高压时钟和低电压时钟;电平移位器，用于输出通过移位与高电压时钟同步的数据产生的高电压数据;数据载体，用于输出低电压数据 与低电压时钟同步;以及数据中继器，用于响应于外部电压电平检查信号输出高电压数据和低电压数据中的一个。

    Method of manufacturing semiconductor memory device
    29.
    发明授权
    Method of manufacturing semiconductor memory device 失效
    制造半导体存储器件的方法

    公开(公告)号：US06383867B1

    公开(公告)日：2002-05-07

    申请号：US09597601

    申请日：2000-06-20

    Applicant: Jae Young Kim ,  Tae Jin Kang

    Inventor： Jae Young Kim ,  Tae Jin Kang

    IPC: H01L218242

    CPC classification number: H01L28/91 ,  H01L21/3212

    Abstract: A method for forming an inner cylinder type storage electrode of a semiconductor memory device, comprising the steps of: forming a first insulating layer on a substrate; etching the first insulating layer to form a contact hole, thereby exposing a portion of the substrate; forming a conductive film for a storage electrode over the first insulating layer including the contact hole; forming a photosensitive film in a portion of the contact hole over the conductive film; forming a second insulating layer to be completely filled in the contact hole over the photosensitive film; etching the second insulating layer and the conductive film to expose the first insulating layer, thereby forming the storage electrode; and removing the first and second insulating layers and the photosensitive film.

    Abstract translation: 一种用于形成半导体存储器件的内筒型存储电极的方法，包括以下步骤：在衬底上形成第一绝缘层; 蚀刻第一绝缘层以形成接触孔，从而暴露基板的一部分; 在包括所述接触孔的所述第一绝缘层上形成用于存储电极的导电膜; 在导电膜上的接触孔的一部分中形成感光膜; 形成完全填充在感光膜上的接触孔中的第二绝缘层; 蚀刻第二绝缘层和导电膜以暴露第一绝缘层，从而形成存储电极; 以及去除第一和第二绝缘层和感光膜。

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