公开(公告)号：US10133701B2

公开(公告)日：2018-11-20

申请号：US15389544

申请日：2016-12-23

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Vanessa Canac ,  James R. Lundberg

IPC: G06F13/42 ,  G06F1/12 ,  G11C8/18 ,  G11C7/10

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a Joint Test Action Group (JTAG) interface, and a bit lag control element. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network includes replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to adjust a propagation time. The bit lag control element is configured to measure, when an update signal is asserted, the propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a first value on a lag bus that indicates an adjusted propagation time. The bit lag control element includes delay lock control, adjust logic, and a gray encoder. The delay lock control is configured to select one of a plurality of successively delayed versions of the first signal that coincides with the assertion the second signal, and is configured to generate a second value on a lag select bus that indicates the propagation time, where the delay lock control selects the one of a plurality of successively delayed versions of the first signal by incrementing and decrementing bus states of select inputs on a mux, and where the plurality of successively delayed versions includes inputs to the mux, and where the plurality of successively delayed versions includes outputs a first plurality of series-coupled matched inverter pairs. The adjust logic is coupled to the JTAG interface and to the lag select bus, and is configured adjust the second value by the amount prescribed by the JTAG interface to yield a third value that is output to an adjusted lag bus. The gray encoder is configured to gray encode the third value to generate the first value on the lag bus.

公开(公告)号：US10120597B2

公开(公告)日：2018-11-06

申请号：US15333004

申请日：2016-10-24

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Yao-Shun Hung ,  Chin-Yin Tsai ,  Yi-Lin Lai

IPC: G06F9/4401 ,  G06F9/445 ,  G06F11/07 ,  G06F11/14 ,  G06F3/06 ,  G06F11/10

Abstract: A memory chip coupled to a host includes a memory and a controller. The memory is pre-loaded with a plurality of boot images, wherein the boot images have the same content. The controller is coupled to the memory, and processes data transmissions between the memory chip and the host, wherein the controller further determines whether the memory chip enters a boot mode for the first time, and when the memory chip enters the boot mode for the first time, the controller accesses the memory to obtain a correct boot image from the boot images and transmits the correct boot image to the host. Further, each boot image includes a plurality of data blocks, and the controller loads a plurality of correct data blocks from one or more of the boot images to obtain the correct boot image.

公开(公告)号：US10119995B2

公开(公告)日：2018-11-06

申请号：US14149822

申请日：2014-01-08

Applicant: VIA Technologies, Inc.

Inventor： Chen-Yueh Kung ,  Wen-Yuan Chang ,  Wei-Cheng Chen

IPC: G01R1/073 ,  G01R31/02 ,  G01R31/26 ,  G01R31/28 ,  H01L21/66 ,  H01L21/84 ,  H01R12/06

Abstract: A probe card including a circuit board, a transformer, a probe head, and a reinforcement structure is provided. The transformer including a body, a plurality of solder balls, and a plurality of first contact points are disposed on the substrate. The body has a first surface and a second surface, wherein the first surface is located between the circuit board and the second surface. The solder balls are disposed on the first surface, and the first contact points are disposed on the second surface. The probe head is disposed on the second surface. The probe head is electrically connected to the circuit board by the first solder balls. The reinforcement structure is disposed between the probe head and the circuit board.

公开(公告)号：US10103217B2

公开(公告)日：2018-10-16

申请号：US15971218

申请日：2018-05-04

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Sheng-Yuan Lee

IPC: H01L29/00 ,  H01L49/02 ,  H01L23/522 ,  H01L29/06 ,  H01L23/528

Abstract: A semiconductor device includes an insulating layer disposed over a substrate, wherein the insulating layer has a center region. A first winding portion and a second winding portion are electrically connected to the first winding portion, disposed in a first level of the insulating layer and surrounding the center region, wherein each of the first winding portion and the second winding portion comprises a plurality of conductive lines arranged from the inside to the outside. A first extending conductive line and a second extending conductive line partially surround the first extending conductive line, and are disposed in the first level of the insulating layer, wherein the first winding portion and the second winding portion surround the first extending conductive line and the second extending conductive line. A third extending conductive line is disposed in a second level of the insulating layer and surrounding the center region.

公开(公告)号：US10079047B2

公开(公告)日：2018-09-18

申请号：US15389795

申请日：2016-12-23

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Vanessa Canac ,  James R. Lundberg

IPC: G06F1/12 ,  G11C7/10 ,  G06F13/42 ,  G11C8/18 ,  G06F13/362 ,  G06F13/40

CPC classification number: G11C7/1072 ,  G06F1/12 ,  G06F13/3625 ,  G06F13/4068 ,  G06F13/4217 ,  G06F13/4243 ,  G11C8/18

Abstract: A method is provided that compensates for misalignment on a synchronous data bus. The method includes: replicating propagation path lengths, loads, and buffering of a radial distribution network for a strobe; receiving a first signal, and generating a second signal by employing the replicated propagation path lengths, loads, and buffering; when an update signal is asserted, when an update signal is asserted, measuring a propagation time beginning with assertion of the first signal and ending with assertion of the second signal by selecting one of a plurality of successively delayed versions of the first signal that coincides with the assertion of the second signal, wherein said selecting comprises incrementing and decrementing bus states of select inputs on a mux, wherein the plurality of successively delayed versions of the first signal comprises inputs to the mux; gray encoding a value on a lag bus that indicates the propagation time; and receiving one of a plurality of radially distributed strobes and a data bit, and delaying registering of the data bit by the propagation time. The receiving includes generating successively delayed versions of the data bit; receiving the value on the lag bus, and selecting one of the successively delayed versions of the data bit that corresponds to the value; and registering the state of the one of the successively delayed versions of the data bit upon assertion of one of a plurality of radially distributed strobe signals.

公开(公告)号：US10061735B2

公开(公告)日：2018-08-28

申请号：US15059227

申请日：2016-03-02

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Wei-Yu Wang ,  Yu-Chung Wei ,  Yinglien Cheng

IPC: G06F13/36 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F11/30

CPC classification number: G06F13/4072 ,  G06F13/4282 ,  G06F13/4295 ,  G06F2213/0042

Abstract: A USB chipset coupled between a first device and a second device is provided. A data processing unit is coupled to the first device and generates a plurality of transmission information according to first information provided by the first device. A transmitting unit is coupled to the data processing unit to transmit the transmission information to the second device and includes a converting module, a first output driving module, a second output driving module, and a transmitting-terminal selecting module. The converting module is coupled to the data processing unit to receive the transmission information in parallel and serially outputs the transmission information. The first output driving module is coupled to a first pin set. The second output driving module is coupled to a second pin set. The transmitting-terminal selecting module is coupled between the converting module and the first and second output driving modules.

公开(公告)号：US20180225305A1

公开(公告)日：2018-08-09

申请号：US15937879

申请日：2018-03-28

Applicant: VIA Technologies, Inc.

Inventor： Guo-Feng Zhang ,  Yi-Fei Zhu

IPC: G06F17/30

CPC classification number: G06F16/29 ,  G06F16/313 ,  G06F16/322

Abstract: A method for displaying landmark data from a search of a place name keyword, the method includes: inputting the place name keyword to a server to search for a plurality of landmark data, wherein each of the landmark data comprises fields of a landmark name, an objective level category, an address, and an address quoting frequency; sorting the landmark data by an electronic device to a display order, based on a characterized parameter for each of the landmark, wherein the characterized parameter is calculated based on at least a publicity, wherein the publicity is a calculation of the objective level category and the address quoting frequency with respectively weighting to the objective level category and the address quoting frequency; and displaying the landmark data by the electronic device according to the display order.

公开(公告)号：US10041999B2

公开(公告)日：2018-08-07

申请号：US15411063

申请日：2017-01-20

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Shih-Hao Chen

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31707 ,  G01R31/31716 ,  G01R31/31723 ,  G01R31/31724 ,  G01R31/3177 ,  G01R31/3187

Abstract: A built-in self-test mechanism for an interface chip. During a loopback test procedure, a transmission terminal of the interface chip is coupled back to the interface chip by a reception terminal of the interface chip and a loopback test circuit within the interface chip generates a test sequence which includes a synchronization section and a section of repeated test code. The test sequence is scrambled by a scrambler and then is transmitted via the transmission terminal and looped back to the reception terminal. The signal looped back to the reception terminal is processed by an equalizer and descrambled by a descrambler to be further checked by the loopback test circuit for determining whether the interface chip is functioning normally. The dynamically-changed keys used in the scrambler and the descrambler are synchronized according to the synchronization section. The equalizer is optimized by the scrambled section of repeated test code.

公开(公告)号：US20180165010A1

公开(公告)日：2018-06-14

申请号：US15378044

申请日：2016-12-14

Applicant: VIA Technologies, Inc.

Inventor： Ying Yu Tai ,  Jiangli Zhu

IPC: G06F3/06 ,  G11C16/34 ,  G06F12/02

Abstract: A non-volatile memory (NVM) apparatus and an iteration sorting method thereof are provided. The NVM apparatus performs the iteration sorting method to select one target block from a plurality of blocks of a NVM, and to perform a management operation on the target block. The iteration sorting method includes: selecting a plurality of candidate blocks among the blocks of the NVM to join into a sorting set, sorting all of the candidate blocks in the sorting set according to metadata, picking one candidate block with maximum (or minimum) metadata from the sorting set to serve as the target block, and keeping M candidate blocks in the sorting set and discarding the rest of the candidate blocks from the sorting set.

公开(公告)号：US20180138639A1

公开(公告)日：2018-05-17

申请号：US15640599

申请日：2017-07-03

Applicant: VIA Technologies, Inc.

Inventor： Sheng-Yuan Lee

IPC: H01R13/6585 ,  H01R24/28 ,  H01R12/53 ,  H01R12/72

CPC classification number: H01R13/6585 ,  H01R12/53 ,  H01R12/722 ,  H01R12/727 ,  H01R13/6588 ,  H01R24/28 ,  H01R24/60 ,  H01R2107/00 ,  H05K1/0219 ,  H05K1/0245 ,  H05K1/0298 ,  H05K3/40 ,  H05K2201/0723

Abstract: A paddle card includes a circuit board, a pad group and first to fourth shielding planes. The circuit board has an upper surface and a lower surface opposite to each other. The pad group is adapted to connect wires of a cable or terminals of a plug, and includes a pair of upper differential pads on the upper surface and a pair of lower differential pads on the lower surface. The pair of upper differential pads is respectively configured corresponding to the pair of lower differential pads in an up and down manner. The first to fourth shielding planes are stacked at intervals between the upper and lower surfaces in sequence. An orthogonal projection of a second opening of the second shielding plane on a geometric plane that a pair of third openings of the third shielding plane is located in is separate from the pair of third openings.