公开(公告)号：US09478646B2

公开(公告)日：2016-10-25

申请号：US13192385

申请日：2011-07-27

Applicant: Anup Bhalla ,  Madhur Bobde ,  Yongping Ding ,  Xiaotian Zhang ,  Yueh-Se Ho

Inventor： Anup Bhalla ,  Madhur Bobde ,  Yongping Ding ,  Xiaotian Zhang ,  Yueh-Se Ho

IPC: H01L29/739 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7395 ,  H01L21/2636 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/761 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/66333

Abstract: A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.

Abstract translation: 用于制造阳极短路场效应绝缘栅双极晶体管（IGBT）的方法包括选择性地形成具有相反导电类型的第一和第二半导体注入区。 可以将第二导电类型的场阻挡层生长到衬底或植入衬底中。 外延层可以在衬底上或场停止层上生长。 在外延层内形成一个或多个绝缘栅双极晶体管（IGBT）元件单元。

公开(公告)号：US20160056098A9

公开(公告)日：2016-02-25

申请号：US14204019

申请日：2014-03-11

Applicant: Yan Xun Xue ,  Yueh-Se Ho ,  Yongping Ding

Inventor： Yan Xun Xue ,  Yueh-Se Ho ,  Yongping Ding

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L23/36

CPC classification number: H01L23/49582 ,  H01L23/36 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49861 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/83486 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/013 ,  H01L2924/05432 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices.

公开(公告)号：US20150262925A1

公开(公告)日：2015-09-17

申请号：US14204019

申请日：2014-03-11

Applicant: Yan Xun Xue ,  Yueh-Se Ho ,  Yongping Ding

Inventor： Yan Xun Xue ,  Yueh-Se Ho ,  Yongping Ding

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L23/36

CPC classification number: H01L23/49582 ,  H01L23/36 ,  H01L23/4334 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49861 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/83486 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/013 ,  H01L2924/05432 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices.

Abstract translation: 半导体器件包括具有覆盖铝合金引线框架的暴露部分的钝化层的铝合金引线框架。 由于铝合金是低成本材料，其硬度和柔韧性适用于冲压，弯曲，成型等变形过程，铝合金引线框架适合批量生产; 此外，由于其重量比铜或铁镍材料低得多，因此铝合金引线框对于半导体器件的生产非常方便。

公开(公告)号：US08785279B2

公开(公告)日：2014-07-22

申请号：US13561523

申请日：2012-07-30

Applicant: Anup Bhalla ,  Hamza Yilmaz ,  Madhur Bobde ,  Lingpeng Guan ,  Jun Hu ,  Jongoh Kim ,  Yongping Ding

Inventor： Anup Bhalla ,  Hamza Yilmaz ,  Madhur Bobde ,  Lingpeng Guan ,  Jun Hu ,  Jongoh Kim ,  Yongping Ding

IPC: H01L21/336

CPC classification number: H01L29/0634 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/404 ,  H01L29/407 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor power device formed in a semiconductor substrate comprising a highly doped region near a top surface of the semiconductor substrate on top of a lightly doped region supported by a heavily doped region. The semiconductor power device further comprises source trenches opened into the highly doped region filled with conductive trench filling material in electrical contact with the source region near the top surface. The semiconductor power device further comprises buried P-regions disposed below the source trenches and doped with dopants of opposite conductivity from the highly doped region. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract translation: 一种形成在半导体衬底中的半导体功率器件，包括在由重掺杂区域支撑的轻掺杂区域的顶部附近的半导体衬底的顶表面附近的高掺杂区域。 所述半导体功率器件还包括向所述高掺杂区域开放的源极沟槽，所述源极沟槽填充有与所述顶部表面附近的所述源极区域电接触的导电沟槽填充材料。 半导体功率器件还包括设置在源沟槽下方并且掺杂有与高掺杂区域相反导电性的掺杂剂的掩埋P区。 要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开内容的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US20130020671A1

公开(公告)日：2013-01-24

申请号：US13135982

申请日：2011-07-19

Applicant: Yeehang Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

Inventor： Yeehang Lee ,  Madhur Bobde ,  Yongping Ding ,  Jongoh Kim ,  Anup Bhalla

IPC: H01L29/06 ,  H01L21/76

CPC classification number: H01L29/7811 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7813

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a heavily doped region formed on a lightly doped region and having an active cell area and an edge termination area. The edge termination area comprises a plurality of termination trenches formed in the heavily doped region with the termination trenches lined with a dielectric layer and filled with a conductive material therein. The edge termination further includes a plurality of buried guard rings formed as doped regions in the lightly doped region of the semiconductor substrate immediately adjacent to the termination trenches.

Abstract translation: 本发明公开了一种设置在半导体衬底中的半导体功率器件，包括形成在轻掺杂区域上并具有有源电池区域和边缘端接区域的重掺杂区域。 边缘终止区域包括形成在重掺杂区域中的多个端接沟槽，其中端接沟槽衬有介电层并在其中填充有导电材料。 边缘终端还包括多个掩埋保护环，其形成为紧邻端接沟槽的半导体衬底的轻掺杂区域中的掺杂区域。