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    Dynamic memory
    21.
    发明授权
    Dynamic memory 失效
    动态内存

    公开(公告)号：US5905685A

    公开(公告)日：1999-05-18

    申请号：US951734

    申请日：1997-10-15

    申请人： Masayuki Nakamura ,  Masatoshi Hasegawa ,  Seiji Narui ,  Yousuke Tanaka ,  Shinichi Miyatake ,  Shuichi Kubouchi ,  Kazuhiko Kajigaya

    发明人： Masayuki Nakamura ,  Masatoshi Hasegawa ,  Seiji Narui ,  Yousuke Tanaka ,  Shinichi Miyatake ,  Shuichi Kubouchi ,  Kazuhiko Kajigaya

    IPC分类号： G11C11/407 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

    CPC分类号： G11C11/4074 ,  G11C11/408 ,  G11C11/4087

    摘要： In a dynamic RAM having a memory cell array in which a dynamic memory cell is arranged at an intersection between a word line and one of a pair of bit lines, a select level signal corresponding to a supply voltage and an unselect level signal corresponding to a negative potential lower than circuit ground potential are supplied to the word line. A signal of a memory cell read to the pair of bit lines by a sense amplifier that operates on the circuit ground potential and an internal voltage formed by dropping the supply voltage by an amount equivalent to the threshold voltage of the address select MOSFET is amplified. The dynamic RAM has an oscillator that receives the supply voltage and circuit ground potential and a circuit that receives an oscillation pulse generated by the oscillator to generate the negative potential.

    摘要翻译： 在具有存储单元阵列的动态RAM中，其中动态存储单元布置在字线和一对位线中的一个位线之间的交叉点处，对应于电源电压的选择电平信号和对应于 低于电路接地电位的负电位被提供给字线。 通过由电路接地电位进行工作的读出放大器对一对位线读取的存储单元的信号和通过将电源电压降低等于地址选择MOSFET的阈值电压的量而形成的内部电压被放大。 动态RAM具有接收电源电压和电路接地电位的振荡器，以及接收由振荡器产生的振荡脉冲以产生负电位的电路。

    SAMPLE ANALYZER
    22.
    发明申请
    SAMPLE ANALYZER 有权
    样品分析仪

    公开(公告)号：US20110169837A1

    公开(公告)日：2011-07-14

    申请号：US12986887

    申请日：2011-01-07

    申请人： Rumi TAKATA ,  Yousuke TANAKA ,  Noriyuki NARISADA ,  Junya INOUE

    发明人： Rumi TAKATA ,  Yousuke TANAKA ,  Noriyuki NARISADA ,  Junya INOUE

    IPC分类号： G01N21/00 ,  G06T11/20

    CPC分类号： G01N33/493 ,  G01N15/14 ,  G01N15/1429 ,  G01N2015/008 ,  G01N2015/1493

    摘要： A sample analyzer comprising: a light source for emitting light to particles contained in a measurement sample which is prepared from a reagent and a urine sample collected from a subject; a detector for detecting scattered light and fluorescence which are generated from the particles in the measurement sample; a display; and a controller, wherein the controller executes operations comprising: obtaining particle data based on the scattered light and the fluorescence which are detected from the particles by the detector; and controlling, when the particle data satisfies a predetermined condition, the display to display information indicating a possibility that the subject is infected with an uncomplicated urinary tract infection is disclosed.

    摘要翻译： 1.一种样品分析装置，其特征在于，包括：光源，其对从被检体收集的试剂和尿液样品制备的测定试样中含有的粒子进行发光; 用于检测由测量样品中的颗粒产生的散射光和荧光的检测器; 一个显示器 以及控制器，其中所述控制器执行操作，所述操作包括：基于由所述检测器从所述粒子检测到的散射光和荧光获得粒子数据; 并且当粒子数据满足预定条件时，控制显示器显示指示受试者感染了不复杂的尿路感染的可能性的信息。

    Steering apparatus
    23.
    发明申请
    Steering apparatus 失效
    转向装置

    公开(公告)号：US20090250288A1

    公开(公告)日：2009-10-08

    申请号：US12384181

    申请日：2009-04-01

    申请人： Katsuji Watanabe ,  Yasuo Shimizu ,  Tsuyoshi Matsuo ,  Yousuke Tanaka

    发明人： Katsuji Watanabe ,  Yasuo Shimizu ,  Tsuyoshi Matsuo ,  Yousuke Tanaka

    IPC分类号： B62D5/04

    CPC分类号： B62D3/12 ,  B62D3/126 ,  B62D5/0409 ,  F16H55/0806 ,  F16H55/0853 ,  F16H55/26 ,  Y10T74/1967 ,  Y10T74/19953

    摘要： An electric power steering apparatus 10 has an electric motor 46 for supplying an auxiliary force to a steering force inputted from a steering wheel 16, and transmits the steering force including the auxiliary force to a steered road-wheel 14 at least partially via a rack-and-pinion mechanism 30, thereby performing steering of a vehicle 12. The rack-and-pinion mechanism 30 includes: a pinion 38 provided at a pinion shaft 28 connected to the steering wheel 16; a rack 40 that is provided over a predetermined width at a rack shaft 32 connected to the steered road-wheel 14, and that is engaged with the pinion 38; and a rack guide 70 for urging the rack shaft 32 toward the pinion 38. A pressure angle α1 of a tooth root of the rack 40 is set to be greater than a pressure angle α0 of a tooth tip of the rack 40.

    摘要翻译： 电动助力转向装置10具有用于向从方向盘16输入的转向力提供辅助力的电动机46，并且至少部分地经由机架式转向装置将包括辅助力的转向力传递给转向车轮14， 齿轮齿条机构30包括：小齿轮38，其设置在与方向盘16连接的小齿轮轴28处; 在与转向车轮14连接并与小齿轮38接合的齿条轴32上设置有预定宽度的齿条40; 以及用于将齿条轴32朝向小齿轮38推压的齿条引导件70.齿条40的齿根的压力角α1被设定为大于齿条40的齿尖的压力角α0。

    Apparatus for analyzing particles in urine and method thereof
    25.
    发明申请
    Apparatus for analyzing particles in urine and method thereof 有权
    用于分析尿中颗粒的装置及其方法

    公开(公告)号：US20090050821A1

    公开(公告)日：2009-02-26

    申请号：US11798066

    申请日：2007-05-10

    申请人： Yousuke Tanaka ,  Junya Inoue ,  Masatsugu Ozasa ,  Yasuyuki Kawashima

    发明人： Yousuke Tanaka ,  Junya Inoue ,  Masatsugu Ozasa ,  Yasuyuki Kawashima

    IPC分类号： G01J1/58 ,  A61N5/00

    CPC分类号： G01N21/6486 ,  G01N15/1459 ,  G01N33/493 ,  G01N2015/008 ,  G01N2015/1493 ,  Y10T436/11 ,  Y10T436/113332 ,  Y10T436/114998 ,  Y10T436/117497 ,  Y10T436/12

    摘要： An apparatus, intended for use in analyzing particles in urine is disclosed, that comprising: a sample distribution section for distributing urine samples to a first aliquot and a second aliquot; a first specimen preparing section for preparing a first specimen for measuring urinary particles, containing at least erythrocytes, by mixing a first stain reagent and the first aliquot; a second specimen preparing section for preparing a second specimen for measuring bacteria by mixing a second stain reagent and the second aliquot; and an optical detecting section comprising a light source for irradiating a light to a specimen being supplied, a scattered light receiving element for detecting scattered light emitted from the specimen, and a fluorescence receiving element for detecting fluorescence emitted from the specimen. A method intended for use in analyzing particles in urine is also disclosed.

    摘要翻译： 公开了一种用于分析尿液中的颗粒的装置，其包括：用于将尿液样品分配到第一等分试样和第二等分试样的样品分配部分; 第一标本制备部分，用于通过混合第一染色剂和第一等分试样来制备用于测量至少包含红细胞的尿颗粒的第一样本; 第二标本制备部，用于通过混合第二染色剂和第二等分试样来制备用于测量细菌的第二样本; 以及光检测部，其包括用于向被供给的样本照射光的光源，用于检测从样本发射的散射光的散射光接收元件和用于检测从样本发出的荧光的荧光接收元件。 还公开了一种用于分析尿液中颗粒的方法。

    Semiconductor memory device
    26.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US07184330B2

    公开(公告)日：2007-02-27

    申请号：US11137583

    申请日：2005-05-26

    申请人： Kenichi Tajima ,  Hiroshi Akasaki ,  Masatoshi Hasegawa ,  Yousuke Tanaka

    发明人： Kenichi Tajima ,  Hiroshi Akasaki ,  Masatoshi Hasegawa ,  Yousuke Tanaka

    IPC分类号： G11C29/00

    CPC分类号： G11C29/84 ,  G11C11/401 ,  G11C11/4091

    摘要： A semiconductor memory device capable of improving the reliability when driving a word line and capable of reducing the access delay due to the defect relief is provided. In order to prevent the multiple selection of a sub-word line of a normal memory mat and a sub-word line of a redundant memory mat, the start of the redundant memory mat is delayed from that of the normal memory mat, and in order to compensate the start delay, the shared circuit is eliminated and the bit line length is reduced in the redundant memory mat. By doing so, the read time of the bit lines is reduced and the signal amount is increased. Consequently, the same activation timing of the sense amplifier as that of the normal memory mat can be used also in the redundant memory mat.

    摘要翻译： 提供一种半导体存储器件，其能够提高驱动字线时的可靠性并且能够减少由于缺陷缓解引起的访问延迟。 为了防止冗余存储器存储器的正常存储器字符串和子字线的子字线的多次选择，冗余存储器衬垫的开始被延迟到正常存储器垫的开始，并且按顺序 为了补偿起始延迟，消除了共享电路，并且在冗余存储器垫中减少了位线长度。 通过这样做，位线的读取时间减少并且信号量增加。 因此，读出放大器与正常存储器垫相同的激活定时也可以用在冗余存储器垫中。

    Semiconductor integrated circuit device
    27.
    发明申请
    Semiconductor integrated circuit device 失效

    公开(公告)号：US20060050583A1

    公开(公告)日：2006-03-09

    申请号：US11262920

    申请日：2005-11-01

    申请人： Yousuke Tanaka ,  Tomofumi Hokari ,  Masatoshi Hasegawa

    发明人： Yousuke Tanaka ,  Tomofumi Hokari ,  Masatoshi Hasegawa

    IPC分类号： G11C7/00

    CPC分类号： H01L27/10882 ,  G11C7/065 ,  G11C7/1042 ,  G11C7/12 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/2227 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10885 ,  H01L27/10891

    摘要： Disclosed herein is a semiconductor integrated circuit device equipped with a memory circuit, which realizes the speeding up of its operation and low power consumption thereof in a simple configuration. At input/output nodes of a sense amplifier including a CMOS latch circuit for performing an amplifying operation in response to an operation timing signal, a pair of first precharge MOSFETs brought to an on state during a precharge period to thereby supply a precharge voltage, and select switch MOSFETs for connecting the input/output nodes and each complementary bit line pair in response to a select signal are provided. A second precharge MOSFET for short-circuiting the complementary bit line pair is provided between the complementary bit line pair. A memory array is provided which includes dynamic memory cells each comprising an address selecting MOSFET and a storage capacitor, each of which is provided between one of the complementary bit line pair and a word line intersecting it. The thickness of a gate insulating film for the second precharge MOSFET is formed thin as compared with that of a gate insulating film for the selecting MOSFETs.

    Semiconductor integrated circuit device operating at high speed and low power consumption
    28.
    发明授权
    Semiconductor integrated circuit device operating at high speed and low power consumption 失效
    半导体集成电路器件工作在高速和低功耗

    公开(公告)号：US06977856B2

    公开(公告)日：2005-12-20

    申请号：US10914291

    申请日：2004-08-10

    申请人： Yousuke Tanaka ,  Tomofumi Hokari ,  Masatoshi Hasegawa

    发明人： Yousuke Tanaka ,  Tomofumi Hokari ,  Masatoshi Hasegawa

    IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108

    CPC分类号： H01L27/10882 ,  G11C7/065 ,  G11C7/1042 ,  G11C7/12 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/2227 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10885 ,  H01L27/10891

    摘要： Disclosed herein is a semiconductor integrated circuit device equipped with a memory circuit, which realizes the speeding up of its operation and low power consumption thereof in a simple configuration. At input/output nodes of a sense amplifier including a CMOS latch circuit for performing an amplifying operation in response to an operation timing signal, a pair of first precharge MOSFETs brought to an on state during a precharge period to thereby supply a precharge voltage, and select switch MOSFETs for connecting the input/output nodes and each complementary bit line pair in response to a select signal are provided. A second precharge MOSFET for short-circuiting the complementary bit line pair is provided between the complementary bit line pair. A memory array is provided which includes dynamic memory cells each comprising an address selecting MOSFET and a storage capacitor, each of which is provided between one of the complementary bit line pair and a word line intersecting it. The thickness of a gate insulating film for the second precharge MOSFET is formed thin as compared with that of a gate insulating film for the selecting MOSFETs.

    摘要翻译： 这里公开了一种配备有存储电路的半导体集成电路装置，其以简单的配置实现其操作的加速和低功耗。 在包括用于响应于操作定时信号执行放大操作的CMOS锁存电路的读出放大器的输入/输出节点处，一对第一预充电MOSFET在预充电期间变为导通状态，从而提供预充电电压，以及 提供了用于连接输入/输出节点和响应于选择信号的每个互补位线对的选择开关MOSFET。 在互补位线对之间提供用于短路互补位线对的第二预充电MOSFET。 提供了一种存储器阵列，其包括每个包括地址选择MOSFET和存储电容器的动态存储器单元，每个存储器单元设置在互补位线对之一和与其相交的字线之间。 与用于选择MOSFET的栅极绝缘膜相比，用于第二预充电MOSFET的栅极绝缘膜的厚度形成得较薄。

    Semiconductor integrated circuit device
    29.
    发明申请
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US20050265096A1

    公开(公告)日：2005-12-01

    申请号：US11136510

    申请日：2005-05-25

    申请人： Tadahiro Obara ,  Masatoshi Hasegawa ,  Yousuke Tanaka ,  Tomofumi Hokari ,  Kenichi Tajima

    发明人： Tadahiro Obara ,  Masatoshi Hasegawa ,  Yousuke Tanaka ,  Tomofumi Hokari ,  Kenichi Tajima

    IPC分类号： H01L27/108 ,  G11C7/00 ,  G11C7/12 ,  G11C11/401 ,  G11C11/409 ,  H01L21/8242 ,  H01L27/105

    CPC分类号： G11C7/12 ,  G11C2207/005 ,  H01L27/105 ,  H01L27/10897

    摘要： A DRAM whose operation is sped up and power consumption is reduced is provided. A pair of precharge MOSFETs for supplying a precharge voltage to a pair of input/output nodes of a CMOS sense amplifier is provided; the pair of input/output nodes are connected to a complementary bit-line pair via a selection switch MOSFET; a first equalize MOSFET is provided between the complementary bit-line pair for equalizing them; a memory cell is provided between one of the complementary bit-line pair and a word line intersecting with it; gate insulators of the selection switch MOSFETs and first equalize MOSFET are formed by first film thickness; a gate insulator of the precharge MOSFET is formed by second film thickness thinner than the first film thickness; a precharge signal corresponding to a power supply voltage is supplied to the precharge MOSFET; and an equalize signal and a selection signal corresponding to a boost voltage are supplied to the first equalize MOSFET and the selection switch MOSFET, respectively.

    摘要翻译： 提供了其操作加快并且功耗降低的DRAM。 提供一对用于向CMOS读出放大器的一对输入/输出节点提供预充电电压的预充电MOSFET; 一对输入/输出节点经由选择开关MOSFET连接到互补位线对; 在互补位线对之间提供第一均衡MOSFET以使它们均衡; 在互补位线对之一和与其相交的字线之间提供存储单元; 选择开关MOSFET和第一均衡MOSFET的栅极绝缘体由第一膜厚度形成; 预充电MOSFET的栅极绝缘体由比第一膜厚度薄的第二膜厚形成; 对应于电源电压的预充电信号被提供给预充电MOSFET; 并且将均衡信号和对应于升压电压的选择信号分别提供给第一均衡MOSFET和选择开关MOSFET。