公开(公告)号：US11720266B2

公开(公告)日：2023-08-08

申请号：US17591924

申请日：2022-02-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： William R. Alverson ,  Amitabh Mehra ,  Anil Harwani ,  Jerry A. Ahrens ,  Grant E. Ley ,  Jayesh Joshi

IPC: G06F3/06 ,  G11C29/10

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0673 ,  G11C29/10

Abstract: Automatic memory overclocking, including: increasing a memory frequency setting for a memory module until a memory stability test fails; determining an overclocked memory frequency setting including a highest memory frequency setting passing the memory stability test; and generating a profile including the overclocked memory frequency setting.

公开(公告)号：US11435806B2

公开(公告)日：2022-09-06

申请号：US16715184

申请日：2019-12-16

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Jerry A. Ahrens ,  Amitabh Mehra ,  Anil Harwani ,  William R. Alverson ,  Grant E. Ley ,  Charles Sy Lee

IPC: G06F1/3234

Abstract: Automatic voltage reconfiguration in a computer processor including one or more cores includes executing one or more user-specified workloads; determining, based on the user-specified workloads, a respective minimum safe voltage for each core of one or more cores; and modifying a respective voltage configuration for each core of the one or more cores based on the respective minimum safe voltage.

公开(公告)号：US10915330B2

公开(公告)日：2021-02-09

申请号：US15846781

申请日：2017-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Amitabh Mehra ,  Krishna Sai Bernucho

IPC: G06F9/4401

Abstract: A computing device includes a processor having a plurality of cores, a core translation component, and a core assignment component. The core translation component provides a set of registers, one register for each core of the multiple processor cores. The core assignment component includes components to provide a core index to each of the registers of the core translation component according to a core assignment scheme during processor initialization. Process instructions from an operating system are transferred to a respective core based on the core indices.

公开(公告)号：US20240264900A1

公开(公告)日：2024-08-08

申请号：US18625417

申请日：2024-04-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Divya Madapusi Srinivas Prasad ,  Sudhanva Gurumurthi ,  Yasuko Eckert ,  Jeffrey Richard Rearick ,  Sankaranarayanan Gurumurthy ,  Amitabh Mehra ,  Shidhartha Das ,  Alex W. Schaefer ,  Vikram Ramachandra ,  Vilas Sridharan

IPC: G06F11/07 ,  G06F1/30

CPC classification number: G06F11/0793 ,  G06F11/07 ,  G06F1/30 ,  G06F11/0721

Abstract: An exemplary computing device includes a plurality of circuits and/or a plurality of in-situ monitors configured to generate outputs that indicate one or more operating conditions of the circuits. The computing device also includes a system management unit configured to detect a potentially faulty voltage-to-frequency ratio implemented by one of the circuits based at least in part on one or more of the outputs. The system management unit is also configured to modify the potentially faulty voltage-to-frequency ratio based at least in part on one or more of the outputs. Various other devices, systems, and methods are also disclosed.

公开(公告)号：US20240220208A1

公开(公告)日：2024-07-04

申请号：US18147257

申请日：2022-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Jerry Anton Ahrens ,  William Robert Alverson ,  Amitabh Mehra ,  Grant Evan Ley ,  Joshua Taylor Knight ,  Anil Harwani ,  Jayesh Hari Joshi

IPC: G06F7/58

CPC classification number: G06F7/588

Abstract: Induced signal marginality for random number generation is described. In accordance with the described techniques, a pseudorandom number is transmitted across an interface while the interface is operated with settings configured to cause instability in the interface. A random number is received as an output of the interface. The settings configured to cause instability in the interface include overclocked settings of interface operating parameters.

公开(公告)号：US20240211416A1

公开(公告)日：2024-06-27

申请号：US18146920

申请日：2022-12-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Jerry Anton Ahrens ,  William Robert Alverson ,  Joshua Taylor Knight ,  Amitabh Mehra ,  Anil Harwani ,  Grant Evan Ley

IPC: G06F13/16

CPC classification number: G06F13/1668 ,  G06F13/1626 ,  G06F13/1642

Abstract: Physical adjustment to system memory with chipset attached memory is described. In accordance with the described techniques, an indication for making one or more physical adjustments to system memory of a device is received. Contents of the system memory are transferred via a chipset link to a chipset attached memory. The device is operated using the contents from the chipset attached memory while the one or more physical adjustments are made to adjust the system memory. After the one or more physical adjustments, the contents are transferred back from the chipset attached memory to the adjusted system memory via the chipset link.

公开(公告)号：US20230350696A1

公开(公告)日：2023-11-02

申请号：US17732741

申请日：2022-04-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Anil Harwani ,  William Robert Alverson ,  Amitabh Mehra ,  Jerry Anton Ahrens ,  Grant Evan Ley ,  Joshua Taylor Knight

IPC: G06F9/445

CPC classification number: G06F9/44505

Abstract: Real time workload-based system adjustment is described. In accordance with the described techniques, a processor and a memory are operated according to first settings associated with a first workload. A second workload configured to utilize the processor and the memory is detected. The second workload is associated with second settings. Responsive to detecting the second workload, operation of the processor and the memory are adjusted to operate according to the second settings without rebooting.

公开(公告)号：US20230315191A1

公开(公告)日：2023-10-05

申请号：US17708453

申请日：2022-03-30

Applicant: Advanced Micro Devices, Inc.

Inventor： William Robert Alverson ,  Amitabh Mehra ,  Jerry Anton Ahrens ,  Grant Evan Ley ,  Anil Harwani ,  Joshua Taylor Knight

IPC: G06F1/3287 ,  G06F9/445 ,  G06F1/3206

CPC classification number: G06F1/3287 ,  G06F9/44505 ,  G06F1/3206

Abstract: Core activation and deactivation for a multi-core processor is described. In accordance with the described techniques, a processor having multiple cores operates using a first core configuration. A request to switch from the first core configuration to a second core configuration is received. Responsive to the request, a switch from the first core configuration to the second core configuration occurs by adjusting a number of active cores of the processor without rebooting.

公开(公告)号：US11740944B2

公开(公告)日：2023-08-29

申请号：US16711875

申请日：2019-12-12

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Amitabh Mehra ,  Anil Harwani ,  William Robert Alverson ,  Jerry Anton Ahrens, Jr. ,  Charles Sum Yuen Lee ,  John William Abshier

IPC: G06F1/324 ,  G06F9/50 ,  G06F9/4401 ,  G06F1/3287

CPC classification number: G06F9/5094 ,  G06F9/4403 ,  G06F1/324 ,  G06F1/3287

Abstract: A method and apparatus for managing processor functionality includes receiving, by the processor, data relating to one or more environmental conditions. The processor compares the data to pre-existing parameters to determine whether or not the environmental conditions are within the pre-existing parameters for normal operation. If the data are within the pre-existing parameters for normal operation, the processor is operated in a normal operation mode. If the data are outside the pre-existing parameters for normal operation, the processor operates in a second operation mode which is dynamically determined and calibrated during power-on, boot and operation.

公开(公告)号：US11675410B2

公开(公告)日：2023-06-13

申请号：US15949662

申请日：2018-04-10

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Amitabh Mehra

IPC: G06F1/32 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/329

CPC classification number: G06F1/3206 ,  G06F1/324 ,  G06F1/329

Abstract: A monitoring system predicts voltage droops at a processor by monitoring one or more performance characteristics of the processor, selecting a response policy based on the prediction, and adjusting a parameter of the processor. Multiple predictions of voltage droop conditions at different locations of the processor are made simultaneously, with the processor generating one or more responses and resulting in adjusting one or more parameters of the processor. By predicting voltage droop conditions before they occur, the deleterious effects of such droop conditions can be minimized or avoided.