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公开(公告)号：US09194914B2
公开(公告)日：2015-11-24
申请号：US13943405
申请日：2013-07-16
Applicant: Advanced Micro Devices, Inc.
Inventor： Stephen V. Kosonocky , Grady Giles
IPC: G01R31/28 , G01R31/3185
CPC classification number: G01R31/318575 , G01R31/318547
Abstract: Some embodiments of a power supply monitor include a measurement circuit to measure a voltage provided to the power supply monitor, a comparator to compare the voltage to a predetermined voltage threshold, and an interface to provide, during a scan test of a processing device including the power supply monitor, a fault signal in response to the voltage being below the voltage threshold. Some embodiments of a method include providing a first test pattern to one or more power supply monitors associated with one or more circuit blocks in the processing device and capturing a first result generated by the power supply monitor(s) based on the first test pattern. The first result indicates whether a voltage provided to the circuit block(s) is below a voltage threshold.
Abstract translation: 电源监视器的一些实施例包括用于测量提供给电源监视器的电压的测量电路，用于将电压与预定电压阈值进行比较的比较器以及在包括所述电源监视器的处理设备的扫描测试期间提供的接口 电源监视器，响应于电压低于电压阈值的故障信号。 方法的一些实施例包括向与处理设备中的一个或多个电路块相关联的一个或多个电源监视器提供第一测试图案，并且基于第一测试图案捕获由电源监视器产生的第一结果。 第一结果指示提供给电路块的电压是否低于电压阈值。
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公开(公告)号：US20230350484A1
公开(公告)日：2023-11-02
申请号：US18304849
申请日：2023-04-21
Applicant: Advanced Micro Devices, Inc.
Inventor： Mihir Shaileshbhai Doctor , Alexander J. Branover , Benjamin Tsien , Indrani Paul , Christopher T. Weaver , Thomas J. Gibney , Stephen V. Kosonocky , John P. Petry
IPC: G06F1/3287 , G06F1/3296 , G06F1/3234
CPC classification number: G06F1/3287 , G06F1/3296 , G06F1/3278 , G06F1/3265
Abstract: A processing device and method for efficient transitioning to and from a reduced power state is provided. The processing device comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the plurality of components. The power management controller receives an indication that the plurality of components are idle, executes a process to enter a component into a reduced power state in response to receiving an acknowledgement from the component of a request from the power management controller to remove power to the component, and executes a process to exit the component from the reduced power state in response to the component being active.
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公开(公告)号：US20230205297A1
公开(公告)日：2023-06-29
申请号：US17562854
申请日：2021-12-27
Applicant: Advanced Micro Devices, Inc.
Inventor： Alexander J. Branover , Thomas J. Gibney , Stephen V. Kosonocky , Mihir Shaileshbhai Doctor , John P. Petry , Indrani Paul , Benjamin Tsien , Christopher T. Weaver
IPC: G06F1/3206
CPC classification number: G06F1/3206
Abstract: A method and apparatus for managing power states in a computer system includes, responsive to an event received by a processor, powering up a first circuitry. Responsive to the event not being serviceable by the first circuitry, powering up at least a second circuitry of the computer system to service the event.
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公开(公告)号：US11630502B2
公开(公告)日：2023-04-18
申请号：US17390486
申请日：2021-07-30
Applicant: Advanced Micro Devices, Inc.
Inventor： John P. Petry , Alexander J. Branover , Benjamin Tsien , Christopher T. Weaver , Stephen V. Kosonocky , Indrani Paul , Thomas J. Gibney , Mihir Shaileshbhai Doctor
IPC: G06F1/32 , G06F1/3287
Abstract: A disclosed technique includes triggering a change for a first set of one or more functional elements and for a second set of one or more functional elements from a high-power state to a low-power state; saving first state of the first set of one or more functional elements via a first set of one or more save-state elements; saving second state of the second set of one or more functional elements via a second set of one or more save-state elements; powering down the first set of one or more functional elements and the second set of one or more functional elements; and transmitting the first state and the second state to a memory.
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公开(公告)号：US20230101640A1
公开(公告)日：2023-03-30
申请号：US17483698
申请日：2021-09-23
Applicant: Advanced Micro Devices, Inc.
Inventor： Mihir Shaileshbhai Doctor , Alexander J. Branover , Benjamin Tsien , Indrani Paul , Christopher T. Weaver , Thomas J. Gibney , Stephen V. Kosonocky , John P. Petry
IPC: G06F1/3287 , G06F1/3234 , G06F1/3296
Abstract: Devices and methods for linear addressing are provided. A device is provided which comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the components. The power management controller is configured to send one of a request to remove power to the components and a request to reduce power to the components when it is determined that the components are idle, execute a first process of one of removing power and reducing power to the components and entering a reduced power state when an acknowledgement of the request is received and execute a second process of restoring power to the components when one or more of the components are indicated to be active.
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Patent Agency Ranking
公开(公告)号：US10425089B2
公开(公告)日：2019-09-24
申请号：US15850593
申请日：2017-12-21
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Stephen V. Kosonocky , Mikhail Rodionov , Joyce C. Wong
Abstract: A master/slave configuration of a frequency locked Loop (FLL) decouples the process, target voltage, temperature (PVT) tracking goals of locking the loop from adapting the clock frequency in response to voltage droops in the supply. A master oscillator circuit receives a regulated supply voltage and supplies a master oscillator signal. A control circuit supplies a master frequency control signal to control a frequency of the master oscillator signal to a target frequency. A slave oscillator circuit is coupled to a regulated supply voltage and a droopy supply voltage and supplies a slave oscillator signal having a frequency responsive to a slave frequency control signal that is based on the master frequency control signal. The frequency of the second oscillator signal is further responsive to a voltage change of the droopy supply voltage.
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公开(公告)号：US10247770B2
公开(公告)日：2019-04-02
申请号：US15381992
申请日：2016-12-16
Applicant: Advanced Micro Devices, Inc.
Inventor： Abhay Deshpande , Arun S. Iyer , Prasanth K. Vallur , Girish Anathahally Singrigowda , Stephen V. Kosonocky
Abstract: Various embodiments of a gate oxide breakdown detection technique detect gate oxide degradation due to stress on a per part basis without destroying functional circuits for an intended application. Stress on the gate oxide may be applied while nominal drain currents flow through a device, thereby stressing the device under conditions similar to actual operating conditions. The technique is relatively fast and does not require analog amplifiers or tuning of substantial amounts of other additional circuitry as compared to conventional gate oxide breakdown detection techniques.
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公开(公告)号：US09552892B1
公开(公告)日：2017-01-24
申请号：US14927964
申请日：2015-10-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Stephen V. Kosonocky , Krishnan T. Sukumar
IPC: H03M1/00 , G11C27/02 , H03K17/687 , H03K3/3562 , H03K3/356
CPC classification number: G11C27/02 , H03K3/0322 , H03K3/356139 , H03K3/356191 , H03K3/35625
Abstract: A sampling circuit uses an input stage to sample an input signal and a secondary evaluation stage to maintain the output state of the input stage. Once the input stage transitions at a clock transition, the secondary evaluation stage uses regenerative feedback devices to hold the state to help ensure the sampling circuit only switches once during an evaluation.
Abstract translation: 采样电路使用输入级来对输入信号和次级评估级进行采样，以维持输入级的输出状态。 一旦输入级在时钟转换过渡，次级评估级使用再生反馈器件来保持状态，以帮助确保采样电路在评估期间仅切换一次。
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公开(公告)号：US20140298068A1
公开(公告)日：2014-10-02
申请号：US13854434
申请日：2013-04-01
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Stephen V. Kosonocky , Christopher Spence Oliver , Sudha Thiruvengadam , Carson D. Henrion
CPC classification number: G06F1/3287 , Y02D10/171
Abstract: An integrated circuit device includes a first module disposed within a first power domain, a second module disposed in a second power domain that is a sub-domain of the first power domain, first power gating logic, and second power gating logic. The first power gating logic generates a first virtual power supply for the first module. The second power gating logic is powered by the first virtual power supply for generating a second virtual power supply for the second power domain.
Abstract translation: 集成电路装置包括布置在第一功率域内的第一模块，设置在作为第一功率域的子域的第二功率域中的第二模块，第一功率门控逻辑和第二功率门控逻辑。 第一电源门控逻辑为第一模块生成第一虚拟电源。 第二电源门控逻辑由第一虚拟电源供电，用于为第二电源域产生第二虚拟电源。
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公开(公告)号：US12181944B2
公开(公告)日：2024-12-31
申请号：US17562854
申请日：2021-12-27
Applicant: Advanced Micro Devices, Inc.
Inventor： Alexander J. Branover , Thomas J. Gibney , Stephen V. Kosonocky , Mihir Shaileshbhai Doctor , John P. Petry , Indrani Paul , Benjamin Tsien , Christopher T. Weaver
IPC: G06F1/3206
Abstract: A method and apparatus for managing power states in a computer system includes, responsive to an event received by a processor, powering up a first circuitry. Responsive to the event not being serviceable by the first circuitry, powering up at least a second circuitry of the computer system to service the event.
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