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    INSTRUCTION FLOW REGULATOR FOR A PROCESSING UNIT
    22.
    发明申请
    INSTRUCTION FLOW REGULATOR FOR A PROCESSING UNIT 有权

    公开(公告)号：US20250004776A1

    公开(公告)日：2025-01-02

    申请号：US18216201

    申请日：2023-06-29

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Wei Huang ,  ZhongXiang Luo ,  ShengNan Xu ,  LingPeng Jin

    IPC: G06F9/48

    Abstract: A processing unit monitors, over a sliding time window, the number of instructions dispatched for execution at the processing unit. In response to the number of instructions exceeding a threshold, the processing unit throttles (e.g., pauses) the dispatch of instructions for a specified amount of time. The processing unit thus ensures that the number of dispatched instructions does not change too rapidly in too short a period of time reducing the likelihood of sudden changes in processing unit current, without unduly impacting the performance of the processing unit across all workloads.

    Method and apparatus for managing power in a thermal couple aware system
    23.
    发明授权
    Method and apparatus for managing power in a thermal couple aware system 有权

    公开(公告)号：US10955884B2

    公开(公告)日：2021-03-23

    申请号：US15071643

    申请日：2016-03-16

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Wei Huang ,  Manish Arora ,  Abhinandan Majumdar ,  Indrani Paul ,  Leonardo de Paula Rosa Piga

    IPC: G06F1/20 ,  G06F1/324 ,  G06F1/329 ,  G06F1/3296

    Abstract: A method and apparatus for managing power in a thermal couple aware system includes determining a candidate configuration mapping based upon one or more criteria, the candidate configuration mapping being a mapping of performance for a candidate configuration of processor sockets in the thermal couple aware system. The candidate configuration mapping is evaluated by comparing the candidate configuration mapping to a stored configuration. If the evaluated candidate configuration mapping provides a better metric than the stored configuration, the stored configuration is updated with the evaluated candidate configuration mapping, and programming instructions are executed in accordance with the candidate configuration mapping if no other configuration mappings are to be determined.

    Setting Operating Points for Circuits in an Integrated Circuit Chip using an Integrated Voltage Regulator Power Loss Model
    24.
    发明申请
    Setting Operating Points for Circuits in an Integrated Circuit Chip using an Integrated Voltage Regulator Power Loss Model 审中-公开

    公开(公告)号：US20190296644A1

    公开(公告)日：2019-09-26

    申请号：US16440838

    申请日：2019-06-13

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Wei Huang ,  Miguel Rodriguez ,  Karthik Rao

    IPC: H02M3/158 ,  G05F1/56 ,  G05F1/46 ,  G05F1/575

    Abstract: An apparatus includes an integrated circuit chip with a set of circuits having two or more subsets of circuits; an external voltage regulator separate from the integrated circuit chip; two or more integrated voltage regulators on the integrated circuit chip that each provide an input voltage to a respective subset of the circuits; and a controller. The controller determines, using an integrated voltage regulator power loss model, an electrical power loss for the integrated voltage regulators for a first combination of operating points for the subsets of the circuits. The controller then determines, based on the electrical power loss, a second combination of operating points for the subsets of the circuits that includes an adjustment to an operating point for at least one of the subsets of the circuits that compensates for an electrical power loss of the corresponding integrated voltage regulator. The controller sets an operating point of each of the subsets of the circuits based on the second combination of operating points.

    Determining thermal time constants of processing systems
    25.
    发明授权
    Determining thermal time constants of processing systems 有权

    公开(公告)号：US10281964B2

    公开(公告)日：2019-05-07

    申请号：US15010965

    申请日：2016-01-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Can Hankendi ,  Manish Arora ,  Indrain Paul ,  Wei Huang ,  Srilatha Manne

    IPC: G06F1/20 ,  G06F11/30

    Abstract: A processing system includes one or more processing units to perform operations and one or more sensors to measure a temperature concurrently with the one or more processing units performing the operations. The processing system also includes a controller to receive feedback indicating the temperature and to determine a peak temperature and a thermal time constant for heating of the processing system based on a comparison of the measured temperature to a first temperature that is predicted based on the peak temperature and a previously determined thermal time constant for heating. Some embodiments of the controller can control a performance state of the processing system based on the peak temperature and the thermal time constant for heating of the processing system.

    Setting operating points for circuits in an integrated circuit chip
    26.
    发明授权
    Setting operating points for circuits in an integrated circuit chip 有权

    公开(公告)号：US10097091B1

    公开(公告)日：2018-10-09

    申请号：US15793951

    申请日：2017-10-25

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Wei Huang ,  Yasuko Eckert ,  Xudong An ,  Muhammad Shoaib Bin Altaf ,  Jieming Yin

    IPC: G05F1/00 ,  H02M3/158 ,  G05F1/575 ,  G05F1/46 ,  G05F1/56 ,  H02M1/00

    Abstract: The described embodiments include an apparatus that controls voltages for an integrated circuit chip having a set of circuits. The apparatus includes a switching voltage regulator separate from the integrated circuit chip and two or more low dropout (LDO) regulators fabricated on the integrated circuit chip. The switching voltage regulator provides an output voltage that is received as an input voltage by each of the two or more LDO regulators, and each of the two or more LDO regulators provides a local output voltage, each local output voltage received as a local input voltage by a different subset of the circuits in the set of circuits. During operation, a controller sets an operating point for each of the subsets of circuits based on a combined power efficiency for the subsets of the circuits and the LDO regulators, each operating point including a corresponding frequency and voltage.

    TEMPERATURE-AWARE TASK SCHEDULING AND PROACTIVE POWER MANAGEMENT
    27.
    发明申请
    TEMPERATURE-AWARE TASK SCHEDULING AND PROACTIVE POWER MANAGEMENT 审中-公开

    公开(公告)号：US20170371719A1

    公开(公告)日：2017-12-28

    申请号：US15192784

    申请日：2016-06-24

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Abhinandan Majumdar ,  Brian J. Kocoloski ,  Leonardo Piga ,  Wei Huang ,  Yasuko Eckert

    IPC: G06F9/50 ,  G06F1/32

    CPC classification number: G06F9/4893 ,  G06F1/206 ,  G06F1/329 ,  G06F9/5094 ,  Y02D10/24

    Abstract: Systems, apparatuses, and methods for performing temperature-aware task scheduling and proactive power management. A SoC includes a plurality of processing units and a task queue storing pending tasks. The SoC calculates a thermal metric for each pending task to predict an amount of heat the pending task will generate. The SoC also determines a thermal gradient for each processing unit to predict a rate at which the processing unit's temperature will change when executing a task. The SoC also monitors a thermal margin of how far each processing unit is from reaching its thermal limit. The SoC minimizes non-uniform heat generation on the SoC by scheduling pending tasks from the task queue to the processing units based on the thermal metrics for the pending tasks, the thermal gradients of each processing unit, and the thermal margin available on each processing unit.

    BALANCING COMPUTATION AND COMMUNICATION POWER IN POWER CONSTRAINED CLUSTERS
    28.
    发明申请
    BALANCING COMPUTATION AND COMMUNICATION POWER IN POWER CONSTRAINED CLUSTERS 有权

    公开(公告)号：US20170160781A1

    公开(公告)日：2017-06-08

    申请号：US14959669

    申请日：2015-12-04

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Leonardo Piga ,  Indrani Paul ,  Wei Huang

    IPC: G06F1/32

    CPC classification number: G06F1/3203 ,  G06F1/3206 ,  G06F1/3287 ,  Y02D10/171

    Abstract: Systems, apparatuses, and methods for balancing computation and communication power in power constrained environments. A data processing cluster with a plurality of compute nodes may perform parallel processing of a workload in a power constrained environment. Nodes that finish tasks early may be power-gated based on one or more conditions. In some scenarios, a node may predict a wait duration and go into a reduced power consumption state if the wait duration is predicted to be greater than a threshold. The power saved by power-gating one or more nodes may be reassigned for use by other nodes. A cluster agent may be configured to reassign the unused power to the active nodes to expedite workload processing.

    SYSTEM AND METHOD FOR DETERMINING CONCURRENCY FACTORS FOR DISPATCH SIZE OF PARALLEL PROCESSOR KERNELS
    29.
    发明申请
    SYSTEM AND METHOD FOR DETERMINING CONCURRENCY FACTORS FOR DISPATCH SIZE OF PARALLEL PROCESSOR KERNELS 有权
    用于确定并行处理器卡尺的分配因子的系数和方法

    公开(公告)号：US20160335143A1

    公开(公告)日：2016-11-17

    申请号：US14710879

    申请日：2015-05-13

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Rathijit Sen ,  Indrani Paul ,  Wei Huang

    IPC: G06F9/54 ,  G06F9/445

    CPC classification number: G06F9/545 ,  G06F9/44505 ,  Y02D10/43

    Abstract: Disclosed is a method of determining concurrency factors for an application running on a parallel processor. Also disclosed is a system for implementing the method. In an embodiment, the method includes running at least a portion of the kernel as sequences of mini-kernels, each mini-kernel including a number of concurrently executing workgroups. The number of concurrently executing workgroups is defined as a concurrency factor of the mini-kernel. A performance measure is determined for each sequence of mini-kernels. From the sequences, a particular sequence is chosen that achieves a desired performance of the kernel, based on the performance measures. The kernel is executed with the particular sequence.

    Abstract translation: 公开了一种确定并行处理器上运行的应用程序的并发因子的方法。 还公开了一种用于实现该方法的系统。 在一个实施例中，该方法包括将内核的至少一部分作为小型内核的序列运行，每个小型内核包括多个并发执行的工作组。 并发执行工作组的数量被定义为小型内核的并发因子。 针对每个小型内核序列确定性能指标。 从序列中，基于性能测量，选择实现内核所需性能的特定序列。 内核以特定顺序执行。

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