公开(公告)号：US20140281190A1

公开(公告)日：2014-09-18

申请号：US13803769

申请日：2013-03-14

Applicant: APPLE INC.

Inventor： Harshavardhan Kaushikkar

IPC: G06F12/08

CPC classification number: G06F12/0815 ,  G06F3/00 ,  G06F9/4411 ,  G06F11/073 ,  G06F11/0751 ,  G06F13/102

Abstract: An apparatus for processing and tracking the progress of coherency transactions in a computing system is disclosed. The apparatus may include a finite-element state machine, a processor, and a scoreboard circuit. The finite-element state machine may be configured to track the progress of a transaction as well as detect errors during the processing of the transaction. The processor may be configured to transmit coherence requests dependent upon the transaction. The scoreboard circuit may be configured to track the requests and associate responses.

Abstract translation: 公开了一种用于处理和跟踪计算系统中的一致性事务的进展的装置。 该装置可以包括有限元状态机，处理器和记分板电路。 有限元状态机可以被配置为跟踪事务的进程以及在事务处理期间检测错误。 处理器可以被配置为发送依赖于该事务的一致性请求。 记分板电路可以被配置为跟踪请求并关联响应。

公开(公告)号：US20140181419A1

公开(公告)日：2014-06-26

申请号：US13724955

申请日：2012-12-21

Applicant: APPLE INC.

Inventor： Gurjeet S. Saund ,  Harshavardhan Kaushikkar ,  Benjamin K. Dodge

IPC: G06F12/08

CPC classification number: G06F13/385 ,  G06F13/28 ,  H04L47/10

Abstract: Systems and methods for preventing excessive buffering of transactions in a coherence point. The coherence point uses a lookahead mechanism to determine if there are enough credits from the memory controller for forwarding the outstanding transactions stored in the IRQ. If there are not enough credits, then the coherence point prevents the switch fabric from forwarding additional transactions to the coherence point. By preventing excessive buffering in the IRQ, the QoS-based ordering of transactions performed by the switch fabric is preserved.

Abstract translation: 在一致性点防止交易过度缓冲的系统和方法。 相干点使用前瞻机制来确定存储器控制器中是否有足够的信用来转发存储在IRQ中的未完成事务。 如果没有足够的积分，则相干点可以防止交换结构将附加事务转发到相干点。 通过防止IRQ中的过度缓冲，交换结构执行的事务的基于QoS的排序得以保留。

公开(公告)号：US20240411695A1

公开(公告)日：2024-12-12

申请号：US18739055

申请日：2024-06-10

Applicant: Apple Inc.

Inventor： Per H. Hammarlund ,  Eran Tamari ,  Lior Zimet ,  Sergio Kolor ,  Sergio Tota ,  Sagi Lahav ,  James Vash ,  Gaurav Garg ,  Jonathan M. Redshaw ,  Steven R. Hutsell ,  Harshavardhan Kaushikkar ,  Shawn M. Fukami

IPC: G06F12/0831 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/109 ,  G06F12/128 ,  G06F13/16 ,  G06F13/28 ,  G06F13/40 ,  G06F15/173 ,  G06F15/78

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

公开(公告)号：US11824795B2

公开(公告)日：2023-11-21

申请号：US17455321

申请日：2021-11-17

Applicant: Apple Inc.

Inventor： Rohit K. Gupta ,  Gregory S. Mathews ,  Harshavardhan Kaushikkar ,  Jeonghee Shin ,  Rohit Natarajan

IPC: H04L12/801 ,  H04L47/80 ,  H04L47/25 ,  H04L47/10

CPC classification number: H04L47/805 ,  H04L47/25 ,  H04L47/39

Abstract: Techniques are disclosed relating to merging virtual communication channels in a portion of a computing system. In some embodiments, a communication fabric routes first and second classes of traffic with different quality-of-service parameters, using a first virtual channel for the first class and a second virtual channel for the second class. In some embodiments, a memory controller communicates, via the fabric, using a merged virtual channel configured to handle traffic from both the first virtual channel and the second virtual channel. In some embodiments, the system limits the rate at which an agent is allowed to transmit requests of the second class of traffic, but requests by the agent for the first class of traffic are not rate limited. Disclosed techniques may improve independence of virtual channels, relative to sharing the same channel in an entire system, without unduly increasing complexity.

公开(公告)号：US20230367510A1

公开(公告)日：2023-11-16

申请号：US18318672

申请日：2023-05-16

Applicant: Apple Inc.

Inventor： Steven Fishwick ,  Lior Zimet ,  Harshavardhan Kaushikkar

IPC: G06F3/06 ,  G06F12/1018 ,  G06F13/16 ,  G06F12/0871 ,  G06F12/1045 ,  G06F12/06 ,  G06F12/0882 ,  G06F12/02

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/0683 ,  G06F12/0238 ,  G06F12/0646 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1018 ,  G06F12/1054 ,  G06F12/1063 ,  G06F13/1668

Abstract: In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.

公开(公告)号：US20230350828A1

公开(公告)日：2023-11-02

申请号：US18309192

申请日：2023-04-28

Applicant: Apple Inc.

Inventor： Sergio Kolor ,  Sergio V. Tota ,  Tzach Zemer ,  Sagi Lahav ,  Jonathan M. Redshaw ,  Per H. Hammarlund ,  Eran Tamari ,  James Vash ,  Gaurav Garg ,  Lior Zimet ,  Harshavardhan Kaushikkar ,  Steven Fishwick ,  Steven R. Hutsell ,  Shawn M. Fukami

IPC: G06F15/173 ,  G06F13/40

CPC classification number: G06F13/4027 ,  G06F13/4022 ,  G06F15/17375 ,  G06F15/17381

Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.

公开(公告)号：US11803471B2

公开(公告)日：2023-10-31

申请号：US17821312

申请日：2022-08-22

Applicant: Apple Inc.

Inventor： Per H. Hammarlund ,  Lior Zimet ,  Sergio Kolor ,  Sagi Lahav ,  James Vash ,  Gaurav Garg ,  Tal Kuzi ,  Jeffry E. Gonion ,  Charles E. Tucker ,  Lital Levy-Rubin ,  Dany Davidov ,  Steven Fishwick ,  Nir Leshem ,  Mark Pilip ,  Gerard R. Williams, III ,  Harshavardhan Kaushikkar ,  Srinivasa Rangan Sridharan

IPC: G06F12/08 ,  G06F12/0831 ,  G06F12/128 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/109 ,  G06F13/28 ,  G06F13/16 ,  G06F13/40 ,  G06F15/173 ,  G06F15/78

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/109 ,  G06F12/128 ,  G06F13/161 ,  G06F13/1668 ,  G06F13/28 ,  G06F13/4068 ,  G06F15/17368 ,  G06F15/7807 ,  G06F2212/305 ,  G06F2212/657

Abstract: An integrated circuit (IC) including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. For example, the IC may include an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices; and an off-chip interconnect coupled to the interconnect fabric and configured to couple the interconnect fabric to a corresponding interconnect fabric on another instance of the integrated circuit, wherein the interconnect fabric and the off-chip interconnect provide an interface that transparently connects the one or more memory controller circuits, the processor cores, graphics processing units, and peripheral devices in either a single instance of the integrated circuit or two or more instances of the integrated circuit.

公开(公告)号：US11693585B2

公开(公告)日：2023-07-04

申请号：US17353349

申请日：2021-06-21

Applicant: Apple Inc.

Inventor： Steven Fishwick ,  Lior Zimet ,  Harshavardhan Kaushikkar

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1045 ,  G06F12/06 ,  G06F12/1018 ,  G06F13/16

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0683 ,  G06F12/0238 ,  G06F12/0646 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1018 ,  G06F12/1054 ,  G06F12/1063 ,  G06F13/1668

Abstract: In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.

公开(公告)号：US20230053530A1

公开(公告)日：2023-02-23

申请号：US17821305

申请日：2022-08-22

Applicant: Apple Inc.

Inventor： Per H. Hammarlund ,  Eran Tamari ,  Lior Zimet ,  Sergio Kolor ,  Sergio V. Tota ,  Sagi Lahav ,  James Vash ,  Gaurav Garg ,  Jonathan M. Redshaw ,  Steven R. Hutsell ,  Harshavardhan Kaushikkar ,  Shawn M. Fukami

IPC: G06F15/173 ,  G06F15/78 ,  G06F13/16 ,  G06F13/40

Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.

公开(公告)号：US11550716B2

公开(公告)日：2023-01-10

申请号：US17648071

申请日：2022-01-14

Applicant: Apple Inc.

Inventor： Gaurav Garg ,  Sagi Lahav ,  Lital Levy-Rubin ,  Gerard Williams, III ,  Samer Nassar ,  Per H. Hammarlund ,  Harshavardhan Kaushikkar ,  Srinivasa Rangan Sridharan ,  Jeff Gonion ,  James Vash

IPC: G06F12/00 ,  G06F12/06 ,  G06F12/0891 ,  G06F9/46 ,  G06F13/16 ,  G06F12/0831

Abstract: Techniques are disclosed relating to an I/O agent circuit of a computer system. The I/O agent circuit may receive, from a peripheral component, a set of transaction requests to perform a set of read transactions that are directed to one or more of a plurality of cache lines. The I/O agent circuit may issue, to a first memory controller circuit configured to manage access to a first one of the plurality of cache lines, a request for exclusive read ownership of the first cache line such that data of the first cache line is not cached outside of the memory and the I/O agent circuit in a valid state. The I/O agent circuit may receive exclusive read ownership of the first cache line, including receiving the data of the first cache line. The I/O agent circuit may then perform the set of read transactions with respect to the data.