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    Retention voltages for integrated circuits
    21.
    发明授权
    Retention voltages for integrated circuits 有权

    公开(公告)号：US09620200B1

    公开(公告)日：2017-04-11

    申请号：US15081869

    申请日：2016-03-26

    Applicant: ARM Limited

    Inventor： Sanjay Mangal ,  Gus Yeung ,  Martin Jay Kinkade ,  Rahul Mathur ,  Bal S. Sandhu ,  George McNeil Lattimore

    IPC: G11C11/00 ,  G11C11/419 ,  G11C11/413 ,  G11C11/412 ,  H01L27/11

    CPC classification number: G11C11/419 ,  G11C5/148 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417 ,  H01L27/11 ,  H01L27/1104

    Abstract: Various implementations described herein may be directed to retention voltages for integrated circuits. In one implementation, an integrated circuit may include functional circuitry to store data bits, and may also include retention mode circuitry coupled to the functional circuitry to provide retention voltages to the functional circuitry, where the retention mode circuitry may include a first circuitry to provide a first retention voltage to the functional circuitry. The first circuitry may include a first diode device, and may include a first transistor device, a second diode device, or combinations thereof. The retention mode circuitry may also include a second circuitry to provide a second retention voltage to the functional circuitry, where the second circuitry includes second transistor devices. Further, the functional circuitry may be held in a data retention mode when the first retention voltage or the second retention voltage is provided to the functional circuitry.

    Brown-Out Detector
    22.
    发明申请
    Brown-Out Detector 审中-公开
    欠压检测器

    公开(公告)号：US20160334470A1

    公开(公告)日：2016-11-17

    申请号：US14712614

    申请日：2015-05-14

    Applicant: ARM Limited

    Inventor： Bal S. Sandhu ,  James Edward Myers

    IPC: G01R31/40 ,  G01R19/165 ,  G01R19/32 ,  G01R17/00

    CPC classification number: G06F1/28 ,  G01R19/16552 ,  G01R19/32

    Abstract: Various implementations described herein are directed to an integrated circuit for brown-out detection. The integrated circuit may include a first stage configured to receive an input voltage and provide a first voltage independent of temperature while remaining related to the input voltage. The integrated circuit may include a second stage configured to receive the input voltage, receive the first voltage from the first stage, and up-convert the first voltage as input voltage lowers. The second stage may be configured to provide a second voltage corresponding to a differential voltage of the input voltage and the first voltage. The integrated circuit may include a third stage configured to receive the second voltage and provide a high-gain output voltage corresponding to an error signal.

    Abstract translation: 本文描述的各种实现涉及用于欠压检测的集成电路。 集成电路可以包括第一级，其被配置为接收输入电压并提供独立于温度的第一电压，同时保持与输入电压相关。 集成电路可以包括被配置为接收输入电压的第二级，从第一级接收第一电压，并且当输入电压降低时上变换第一电压。 第二级可以被配置为提供对应于输入电压和第一电压的差分电压的第二电压。 集成电路可以包括被配置为接收第二电压并且提供对应于误差信号的高增益输出电压的第三级。

    Apparatus and method for masking power consumption of a processor
    23.
    发明授权
    Apparatus and method for masking power consumption of a processor 有权

    公开(公告)号：US11822705B2

    公开(公告)日：2023-11-21

    申请号：US17536696

    申请日：2021-11-29

    Applicant: Arm Limited

    Inventor： Bal S. Sandhu ,  George McNeil Lattimore ,  Carl Wayne Vineyard

    IPC: H04L29/06 ,  G06F21/75 ,  G06F1/28

    CPC classification number: G06F21/755 ,  G06F1/28

    Abstract: An apparatus for masking power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises power-complementing circuitry configured to provide a second power consumption to directly power-complementing the power consumption associated with the one or more operations of the logic circuitry. The second power consumption complements the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The power-complementing circuitry and the header circuitry are each coupled to the logic circuitry at the common node.

    Apparatus and Method for Masking Power Consumption of a Processor
    24.
    发明申请
    Apparatus and Method for Masking Power Consumption of a Processor 有权

    公开(公告)号：US20220083696A1

    公开(公告)日：2022-03-17

    申请号：US17536696

    申请日：2021-11-29

    Applicant: Arm Limited

    Inventor： Bal S. Sandhu ,  George McNeil Lattimore ,  Carl Wayne Vineyard

    IPC: G06F21/75 ,  G06F1/28

    Abstract: An apparatus for masking power consumption associated with one or more operations of a logic circuitry of a processor. The apparatus comprises power-complementing circuitry configured to provide a second power consumption to directly power-complementing the power consumption associated with the one or more operations of the logic circuitry. The second power consumption complements the power consumption associated with the one or more operations of the logic circuitry. The apparatus further comprises header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry. The power-complementing circuitry and the header circuitry are each coupled to the logic circuitry at the common node.

    Power-on-reset detector
    28.
    发明授权
    Power-on-reset detector 有权
    上电复位检测器

    公开(公告)号：US09473114B1

    公开(公告)日：2016-10-18

    申请号：US14687526

    申请日：2015-04-15

    Applicant: ARM Limited

    Inventor： Bal S. Sandhu ,  James Myers

    IPC: H03L7/00 ,  H03K3/013 ,  H03K17/22 ,  H03K3/3565

    CPC classification number: H03K17/223 ,  H03K3/3565

    Abstract: Various implementations described herein are directed to an integrated circuit for power-on-reset detection. The integrated circuit may include a first stage configured to receive an input voltage signal and provide a triggering signal during ramp of the input voltage signal. The integrated circuit may include a second stage configured to receive the triggering signal from the first stage and provide an output voltage signal during ramp of the input voltage signal via gate leakage through at least one transistor.

    Abstract translation: 本文描述的各种实现涉及用于上电复位检测的集成电路。 集成电路可以包括被配置为接收输入电压信号并且在输入电压信号的斜坡期间提供触发信号的第一级。 集成电路可以包括第二级，其被配置为从第一级接收触发信号，并且在通过至少一个晶体管的栅极泄漏的输入电压信号的斜坡期间提供输出电压信号。

    Controlling voltage generation and voltage comparison
    29.
    发明授权
    Controlling voltage generation and voltage comparison 有权
    控制电压产生和电压比较

    公开(公告)号：US09170282B2

    公开(公告)日：2015-10-27

    申请号：US13895624

    申请日：2013-05-16

    Applicant: ARM LIMITED

    Inventor： Parameshwarappa Anand Kumar Savanth ,  James Edward Myers ,  David Walter Flynn ,  Bal S. Sandhu

    IPC: H03K19/094 ,  G01R19/00 ,  H02M3/07

    CPC classification number: H02M3/157 ,  G01R19/0084 ,  H02M3/07 ,  Y02B70/16

    Abstract: An integrated circuit has voltage generating circuitry for generating an on-chip voltage from a supply voltage in response to clock pulses. Clock control circuitry controls transmission of the clock pulses to the voltage generating circuitry. The clock control circuitry receives a reference voltage and a digital offset value comprising a binary numeric value identifying an offset. The clock control circuitry suppresses transmission of the clock pulses if the on-chip voltage is greater than the sum of the reference voltage and the offset identified by the digital offset value, to reduce power consumption. The offset can be tuned digitally to vary the average level of the on-chip voltage. A similar digital tuning mechanism may be used in a clocked comparator to compare a first voltage with a digitally tunable threshold voltage.

    Abstract translation: 集成电路具有用于响应于时钟脉冲从电源电压产生片上电压的电压产生电路。 时钟控制电路控制时钟脉冲的传输到电压产生电路。 时钟控制电路接收参考电压和包括识别偏移的二进制数值的数字偏移值。 如果片上电压大于参考电压和由数字偏移值识别的偏移的总和，则时钟控制电路抑制时钟脉冲的传输，以减少功耗。 可以数字调整偏移量以改变片内电压的平均电平。 在时钟控制的比较器中可以使用类似的数字调谐机构来将第一电压与数字可调阈值电压进行比较。

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